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ics for consumer electronics tvtext 8-bit microcontroller, romless-version: sda 5250 tvtext 8-bit microcontroller, rom-versions: sda 5251 sda 5252 sda 5254 sda 5255 preliminary data sheet 1998-04-08
sda 525x revision history: current version: 1998-04-08 previous version: users manual 06.97 page (in previous version) page (in current version) subjects (major changes since last revision) the layout of the document has been completely updated. edition 1998-04-08 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1998. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you e get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered.
sda 525x table of contents page semiconductor group 3 1998-04-08 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 pin configuration p-mqfp-80-1 (romless-version) . . . . . . . . . . . . . . . . .8 4.2 pin configuration p-sdip-52-1 (rom-versions) . . . . . . . . . . . . . . . . . . . . .9 4.3 pin configuration p-mqfp-64-1 (rom-versions) . . . . . . . . . . . . . . . . . . .10 4.4 pin configuration p-lcc-84-2 (emulator-version) . . . . . . . . . . . . . . . . . .11 5 pin functions (rom- and romless-version) . . . . . . . . . . . . . . . . . . . . .12 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1 acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1.1 ttx/vps slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1.2 acquisition hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1.3 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 6.1.4 acquisition control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6.2 display generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2.1 display format and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2.2 display cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2.3 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2.4 full screen background colour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2.5 clear page logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2.6 display page addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.2.7 character generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.2.8 on screen display (osd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.2.9 display special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.2.10 sandcastle decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.3 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.3.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.3.1.1 cpu-hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 6.3.1.2 cpu-timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.3.1.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.3.2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.3.2.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.3.2.2 internal data ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.3.2.3 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.3.3 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.3.3.1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.3.4 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 6.3.4.1 interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
sda 525x table of contents page semiconductor group 4 1998-04-08 6.3.4.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 6.3.4.3 interrupt task function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.3.4.4 response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.3.5 processor reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.3.6 ports and i/o-pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.3.7 general purpose timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.3.8 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.3.9 capture compare timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 6.3.10 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.3.10.1 multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 6.3.10.2 baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 6.3.10.3 more about mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 6.3.10.4 more about mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 6.3.10.5 more about modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 6.3.11 pulse width modulation unit (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 6.3.12 analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.3.13 advanced function register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 6.3.14 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 6.3.14.1 notes on data addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 6.3.14.2 notes on program addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . .116 6.3.14.3 instruction set description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 6.3.15 instruction opcodes in hexadecimal order . . . . . . . . . . . . . . . . . . . . . . .122 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 7.2 dc-characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 7.3 ac-characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 8 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 10 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
sda 525x semiconductor group 5 1998-04-08 1 general description the sda 525x contains a slicer for ttx, vps and wss, an accelerating acquisition hardware modul, a display generator for level 1 ttx data and an 8 bit microcontroller running at 333 ns cycle time. the controller with dedicated hardware guarantees flexibility, does most of the internal processing of ttx acquisition, transfers data to/from the external memory interface and receives/transmits data via i 2 c and uart user interfaces. the block diagram shows the internal organization of the sda 525x. the slicer combined with dedicated hardware stores ttx data in a vbi buffer of 1 kbyte. the microcontroller firmware does the total acquisition task (hamming- and parity-checks, page search and evaluation of header control bits) once per field. 2 features acquisition ? feature selection via special function register ? simultaneous reception of ttx, vps and wss ? fixed framing code for vps and ttx ? acquisition during vbi ? direct access to vbi ram buffer ? acquisition of packets x/26, x/27, 8/30 (firmware) ? assistance of all relevant checks (firmware) ? 1-bit framing code error tolerance (switchable) display ? features selectable via special function register ? 50/60 hz display ? level 1 serial attribute display pages ? blanking and contrast reduction output ? 8 direct addressable display pages for sda 5250, sda 5254 and sda 5255 ? 1 direct addressable display page for sda 5251 and sda 5252 ? 12 10 character matrix ? 96 character rom (standard g0 character set) ? 143 national option characters for 11 languages ? 288 characters for x/26 display ? 64 block mosaic graphic characters ? 32 characters for osd in expanded character rom + 32 characters inside osd box ? conceal/reveal ? transparent foreground/background - inside/outside of a box ? contrast reduction inside/outside of a box ? cursor (colour changes from foreground to background colour) ? flash (flash rate 1s)
sda 525x semiconductor group 6 1998-04-08 ? programmable horizontal and vertical sync delay ? full screen background colour in outer screen ? double size / double width / double height characters synchronization ? display synchronization to sandcastle or horizontal sync (hs) and vertical sync (vs) with start-stop-oscillator ? independent clock systems for acquisition, display and controller microcontroller ? 8 bit c500-cpu (8051 compatible) ? 18 mhz internal clock ? 0.33 m s instruction cycle ? parallel 8-bit data and 16...19 - bit address bus (romless-version) ? eight 16-bit data pointer registers (dptr) ? two 16-bit timers ? watchdog timer ? capture compare timer for infrared remote control decoding ? serial interface (uart) ? 256 bytes on-chip ram ? 8 kbyte on-chip display-ram (access via movx) for sda 5250, sda 5254 and sda 5255 ? 1 kbyte on-chip display-ram (access via movx) for sda 5251 and sda 5252 ? 1 kbyte on-chip tvt/vps-acquisition-buffer-ram (access via movx) ? 1 kbyte on-chip extended-ram (access via movx) for sda 5250, sda 5254 and sda 5255 ? 6 channel 8-bit pulse width modulation unit ? 2 channel 14-bit pulse width modulation unit ? 4 multiplexed adc inputs with 8-bit resolution ? one 8-bit i/o port with open drain output and optional i 2 c-bus emulation (port 0) ? two 8-bit multifunctional i/o ports (port 1, port 3) ? one 4-bit port working as digital or analog inputs (port 2) ? one 2-bit i/o port with optional functions ? one 3-bit i/o port with optional ram/rom address expansion up to 512 kbyte (romless-version) C p-sdip-52-1 package or p-mqfp-64-1 for rom-versions (sda 5251, sda 5252, sda 5254, sda 5255) C p-mqfp-80-1 package for romless-version (sda 5250 m) C p-lcc-84-2 package for emulator-version (sda 5250) C 5 v supply voltage
sda 525x semiconductor group 7 1998-04-08 3 block diagram figure 1 block diagram capture compare timer watchdog timer adc pwm vtx, vps slicer acquisition ttc ttd display timing character rom 12 448 ** 10 dual port interface dual port interface vbi buffer 1 k byte 4) ram display c500 cpu memory management unit (mmu) 2) data 3) ram extended program memory rom 1) r g b blan cor cvbs fil1slc fil2slc fil3slc i ref lcin lcout hs / sc vs p3 p2 p1 p0 xtal1, xtal2 d (7:0) psen, ale rd, wr p4.1 (a18), p4.0 (a17) a (16:0) 1) only rom version 2) only romless version 3) only sda 5250, sda 5254 and sda 5255 4) 8 kbyte for sda 5250, sda 5254 and sda 5255 1 kbyte for sda 5251, sda 5252 ueb08124 display generator 1 k byte
sda 525x semiconductor group 8 1998-04-08 4 pin configurations 4.1 pin configuration p-mqfp-80-1 (romless-version) figure 2 pin configuration p-mqfp-80-1 (romless-version) (top view) p0.4 p0.3 p0.1 p0.2 cor lcin lcout r d3 b g blan p2.0 p0.6 p0.5 p0.7 p2.3 p2.1 p2.2 p3.5 p3.6 p3.7 cvbs fil2 fil1 ale xtal2 p1.5 p1.3 p1.4 p1.6 p1.7 n.c. a3 a13 a7 a8 a6 a9 a4 a10 a2 d7 a1 a0 d0 d5 uep08125 p0.0 vs/p4.7 hs/sc p1.2 p1.1 p1.0 xtal1 rst d6 sda 5250 m 60 61 80 21 40 70 30 41 50 20 10 1 a18 / p4.1 a16 a17 / p4.0 dd v ss v p3.1 p3.0 fil3 p3.2 p3.3 p3.4 dda v ssa v ref i ss v dd v d1 d4 d2 a15 a12 a14 a11 a5
sda 525x semiconductor group 9 1998-04-08 4.2 pin configuration p-sdip-52-1 (rom-versions) figure 3 pin configuration p-sdip-52-1 (rom-versions) (top view) sda 5251 sda 5252 sda 5254 sda 5255 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 fil3 fil1 p1.0 p1.1 p1.2 p1.3 p1.5 p1.4 p1.6 rst p1.7 p4.0 p0.7 xtal1 xtal2 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p3.1 fil2 cvbs p2.3 p2.2 p2.1 p2.0 p3.3 lcin lcout cor p3.6 p3.7 p3.5 p3.2 p3.4 hs / sc vs / p4.7 r g b blan p3.0 v dd ss v ss v v dd dda v ssa v i ref uep08126
sda 525x semiconductor group 10 1998-04-08 4.3 pin configuration p-mqfp-64-1 (rom-versions) figure 4 pin configuration p-mqfp-64-1 (rom-versions) (top view) uep09858 39 xtal1 10 p3.6 p2.2 n.c. p2.1 p2.3 cvbs p3.3 62 64 63 1 61 60 59 234 lcin p3.7 lcout 6 5789 fil3 fil2 fil1 p1.0 p1.1 p1.2 p1.3 55 57 58 56 54 53 52 p1.5 47 48 51 50 49 45 46 p1.6 n.c. 42 43 44 n.c. p1.7 rst 40 41 p4.0 xtal2 p3.5 n.c. n.c. p3.4 p3.2 13 11 12 14 15 hs/sc 19 17 18 16 20 21 22 r n.c. vs/p4.7 g b blan 36 37 38 34 35 p0.0 26 23 24 25 27 28 29 p0.7 p3.0 cor p3.1 p0.6 p0.5 p0.4 33 30 32 31 p0.1 p0.3 p0.2 ss v v ss v dd v dd p2.0 n.c. v dd v dd v ss v ss p1.4 ssa v dda v n.c. i ref sda 5251m sda 5252m sda 5254m sda 5255m
sda 525x semiconductor group 11 1998-04-08 4.4 pin configuration p-lcc-84-2 (emulator-version) figure 5 pin configuration p-lcc-84-2 (emulator-version) (top view) uep10154_b 74 11 84 1 ss p3.2 v sda 5250 p1.0 xtal2 xtal1 345678910 v dd rst wr rd ale a17/p4.0 a16 a18/p4.1 83 82 81 80 79 78 77 76 75 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/odd-even p3.1 12 a15 p0.5 53 73 p3.3 13 72 p3.4 14 71 p3.5 15 70 p3.6 16 69 p3.7 17 68 cvbs 18 67 19 66 20 65 fil2 21 64 fil1 22 63 fil3 23 62 24 61 p2.0/ana0 25 60 p2.1/ana1 26 59 p2.2/ana2 27 58 p2.3/ana3 28 57 ene 29 56 stop_ocf 30 55 p0.7 31 54 p0.6 32 p0.4 52 p0.3 51 p0.2 50 p0.1 49 p0.0 48 /p4.7/odd-even 47 hs/sc 46 lcout 45 lcin 44 43 42 cor 41 blan 40 b 39 g 38 r 37 d3 36 d2 35 d4 34 d1 33 dda v ss v v dd i ref ssa v a14 a12 a13 a7 a8 a6 a9 a5 a11 a4 psen a3 a10 a2 a1 d7 a0 d6 d0 d5 s v
sda 525x semiconductor group 12 1998-04-08 5 pin functions (rom- and romless-version) table 1 pin functions (rom- and romless-version) symbol pin no. p-sdip- 52-1 pin no. p-mqfp- 64-1 pin no. p-mqfp- 80-1 pin no. p-lcc-84- 2 input (i) output (o) supply (s) function p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 9 8 7 6 5 4 3 2 34 33 31 30 29 28 27 26 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 i/o i/o i/o i/o i/o i/o i/o i/o port 0 is an 8-bit open drain bidirectional i/o port. port 0 pins that have 1s written to them float; in this state they can be used as high- impedance inputs (e.g. for software driven i 2 c bus). p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 23 22 21 20 19 18 17 16 53 52 51 50 48 47 46 44 11 10 9 8 7 6 5 4 84 83 82 81 80 79 78 77 i/o i/o i/o i/o i/o i/o i/o i/o port 1 is an 8-bit bidirectional multifunctional i/o port with internal pullup resistors. port 1 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs. the secondary functions of port 1 pins are: port bits p1.0 - p1.5 contain the 6 output channels of the 8-bit pulse width modulation unit. port bits p1.6 - p1.7 contain the two output channels of the 14-bit pulse width modulation unit. p2.0 p2.1 p2.2 p2.3 34 33 32 31 1 63 62 61 67 66 65 64 61 60 59 58 i i i i p2.0 - p2.3 are working as digital or analog inputs. xtal2 13 40 14 3 o output of the inverting oscillator amplifier. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left open. xtal1 12 39 15 4 i input to the inverting oscillator amplifier rst 15 42 16 5 i a low level on this pin resets the processor
sda 525x semiconductor group 13 1998-04-08 v dd v ss 11, 37 10, 35 5, 6, 37, 38 2, 3, 35, 36 13, 51 12, 50 2, 43 1, 42 s s power supply voltage ground (0 v) r g b blan cor 47 48 49 50 51 19 20 21 22 23 45 46 47 48 49 37 38 39 40 41 o o o o o red colour signal output green colour signal output blue colour signal output blanking output contrast reduction output p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 52 1 44 36 43 42 41 40 24 25 15 4 14 13 10 9 3 2 80 79 78 77 76 75 76 75 74 73 72 71 70 69 i/o i/o i/o i/o i/o i/o i/o i/o port 3 is an 8-bit bidirectional i/o port with internal pullup resistors. port 3 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs. it also contains the interrupt, timer and serial port input pins. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 3 as follows: - int0 (p3.2): interrupt 0 input/timer 0 gate control input - int1 (p3.3): interrupt 1 input/timer 1 gate control input - t0 (p3.4): counter 0 input - t1 (p3.5): counter 1 input - rxd(p3.6): serial port receive line - txt(p3.7): serial port transmit line attention: p3.6 must not be kept to 0 during reset, otherwise a special test mode will be activated. table 1 pin functions (rom- and romless-version) (contd) symbol pin no. p-sdip- 52-1 pin no. p-mqfp- 64-1 pin no. p-mqfp- 80-1 pin no. p-lcc-84- 2 input (i) output (o) supply (s) function
sda 525x semiconductor group 14 1998-04-08 hs/sc vs/p4.7 cvbs p4.0 p4.1 45 46 30 14 C 16 18 60 41 C 54 55 74 18 20 46 47 68 9 11 i i/o i i/o i/o horizontal sync input (alternative sandcastle sync input) for display vertical sync input for display (alternative port 4.7) cvbs (video signal) input port 4.0 is a bidirectional i/o port with internal pullup resistors. port 4 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs. attention: p4.0 must not be kept to 0 during reset, otherwise a special test mode will be activated. i ref 29 59 73 67 i reference current input for slicer plls v dda v ssa 28 24 58 54 72 68 66 62 s s analog supply voltage for slicer and adc analog ground for slicer and adc fil1 26 56 70 64 i/o pll loop filter i/o for ttx slicing fil2 27 57 71 65 i/o pll loop filter i/o for vps/wss slicing fil3 25 55 69 63 i/o pll loop filter i/o for ttx/vps/wss data slicing lcin lc-out 38 39 7 8 52 53 44 45 i o lcin and lcout are used to connect the external display dot clock frequency reference. table 1 pin functions (rom- and romless-version) (contd) symbol pin no. p-sdip- 52-1 pin no. p-mqfp- 64-1 pin no. p-mqfp- 80-1 pin no. p-lcc-84- 2 input (i) output (o) supply (s) function
sda 525x semiconductor group 15 1998-04-08 table 2 additional pins for romless-version symbol pin nr. p-mqfp-80-1 pin nr. p-lcc-84-2 input (i) output (o) supply (s) function a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 37 35 34 32 31 29 27 25 26 28 33 30 23 24 22 21 19 29 27 26 24 22 20 18 16 17 19 25 21 14 15 13 12 10 o o o o o o o o o o o o o o o o o address bus for external memory d0 d1 d2 d3 d4 d5 d6 d7 39 41 43 44 42 40 38 36 31 33 35 36 34 32 30 28 i/o i/o i/o i/o i/o i/o i/o i/o data bus for external memory stop_ocf ene rd wr ale psen C C C C 17 C 56 57 7 6 8 23 i/o i o o o o control signals for data memory extension and emulation.
sda 525x semiconductor group 16 1998-04-08 6 functional description 6.1 acquisition 6.1.1 ttx/vps slicer the slicer extracts horizontal and vertical sync information and ttx data from the cvbs signal. the slicer includes an analog circuit for sync filtering and data slicing. further there are two analog plls for system clock generation for both ttx and vps. therefore the slicer is able to receive both ttx and vps in succeeding lines of a vertical blanking interval. a third data-pll shifts the phase of the system clock for data sampling. the internal slicer timing signals are generated from the vps-pll. 6.1.2 acquisition hardware the acquisition hardware transforms the sliced bit stream into a byte stream. a framing code check follows to identify a ttx or vps line. if the framing code error tolerance is enabled then one-bit errors will be allowed. for each line in the vbi in which a framingcode is detected, a maximum of 42 bytes (vps: 26 bytes) plus a status word are stored in the vbi-buffer. after framing code detection a status word is generated which informs about the type of data received (ttx or vps) and the signal quality of the tv channel. chapter acquisition status word on page 17 shows the format of this status word. the horizontal and vertical windows in which ttx or vps data are accepted and checked for framing code errors are generated automatically. the vbi buffer data will be analyzed (hamming, parity and acquisition) by the microcontroller and stored in the dual port display ram or the external ram, if selected. this analysis is repeated for every field.
sda 525x semiconductor group 17 1998-04-08 acquisition status word 6.1.3 memory interface the acquisition dual port interface manages the vbi memory write access request from the acquisition hardware and an asynchronous memory access request from the microcontroller. the acquisition hardware delivers the address and data and then a request to the interface. the access of acquisition hardware and controller is under a special arbiter control. the end of data is indicated by the bit lin24st in sfr acqsir. ttx/vps fcer fcok lin.4 lin.3 lin.2 lin.1 lin.0 lin.(4...0) number of tv line in which data was received. this information can be used to realize a software data entry window. 6 lin. (4...0) 22 fcok 1 = framing code ok (vps or ttx). this bit is set always by hardware, because lines with valid framing codes are stored only. this bit is reset by software in vbi-buffer. if reset, it indicates that this line was already processed. fcer 1 = the framing code for ttx lines was accepted with 1-bit- error. for vps lines this bit has no meaning. 0 = for ttx lines the framing code e4 h was detected. ttx/vps 1 = a valid ttx framing code was detected and the data-pll is locked to the ttx frequency. 0 = a valid vps framing code was detected and the data-pll is locked to the vps frequency.
sda 525x semiconductor group 18 1998-04-08 6.1.4 acquisition control registers the following sections gives an overview about special function registers acqms_1, acqms_2 and acqsir, with which slicer and acquisition can be controlled: acquisition mode and status register acqms_1 acquisition mode and status register acqms_2 acquisition mode and status register acqms_1 sfr-address c1 h default after reset: 00 h (msb) (lsb) 0 0 vpse 0 cric.1 cric.0 enert ttxe ttxe 1: enable ttx in lines 6 - 22 enert 1: allow 1 bit error for ttx cric.1 ... cric.0 00: the cri is not included in frc 01: last 2 bits of cri are included in the frc 10: last 4 bits of cri are included in the frc 11: last 8 bits of cri are included in the frc vpse 1: enable vps in line 16. text-reception in this line is automatically disabled comments bits 4, 6 and 7 are not defined, must be set to 0 acquisition mode and status register acqms_2 sfr-address c2 h default after reset: 00 h (msb) (lsb) test.7 test.6 test.5 test.4 test.3 test.2 test.1 test.0 comments all bits have to be set to 0. setting any of these bits will switch on special slicer test modes for production test
sda 525x semiconductor group 19 1998-04-08 acquisition-sync-interrupt-register acqsir acquisition-sync-interrupt- register acqsir sfr-address c0 h default after reset: 00 h (msb) (lsb) evenen evenst lin24en lin24st aviren avirst ahiren ahirst ahirst 1 = acquisition horizontal sync interrupt request. this bit is set by the positive edge of hs. it must be reset by software. ahiren 1 = enable acquisition horizontal sync interrupt request. avirst 1 = acquisition vertical sync interrupt request. this bit is set by the positive edge of vs. it must be reset by software. aviren 1 = enable acquisition vertical sync interrupt request. lin24st 1 = acquisition line 24 interrupt request. acquisition hardware processing in vbi interval is finished. this bit assists the synchronization of acquisition software to the acq- timing. it is set by hardware at the beginning of line 24 and the corresponding line of 2nd field. it is reset by software. lin24en 1 = enable acquisition line 24 interrupt request. evenst 1 = even field interrupt. must be reset by software. evenen 1 = enable even field interrupt requests. comments none
sda 525x semiconductor group 20 1998-04-08 6.2 display generator the display features of sda525x are similar to the siemens sda5248 ttx controller. the display generator reads character addresses and control characters from the display memory, selects the pixel information from the character rom and translates it into rgb values corresponding to the world standard teletext norm. the national option character bits for 11 languages inclusive x/26 characters are also supported. 6.2.1 display format and timing a page consists of 25 rows of 40 characters each. one character covers a matrix of 12 horizontal and 10 vertical pixels. the pixel frequency should be 12 mhz corresponding to 1 m s for one character and 40 m s for one row. a total of 250 tv lines are used for ttx display. the display can be shifted horizontally from 0 m s to 21.33 m s with respect to hs and vertically from line 1 (314) to line 64 (377) with respect to vs. the display position is determined by the registers dhd and dvd. note: to avoid interferences between the subharmonics of the 18 mhz controller clock and the 12 mhz pixel clock, a pixel clock of about 11,5 mhz is recommended. 6.2.2 display cursor a cursor is available which changes foreground to background colour for one character. cursor flash can be realized via software enabling/disabling the cursor. the cursor position is defined by cursor position registers dcrp and dccp. 6.2.3 flash a character background flash (character is changed to background colour) is realized by hardware. the flash frequency is 1 hz with a duty cycle of 32:18. 6.2.4 full screen background colour the sda 525x delivers the new full screen background colour feature. special function register sfr dtim(7-5) includes three bits which define the default background colour for the inner and outer screen area. 6.2.5 clear page logic the clear page logic generates a signal which is interpreted by the character generator to identify non displayable rows. in row 25 specific information is stored by the microcontroller indicating which of the rows 0 - 24 should be interpreted as erased during character generation. at the beginning of each row the special control characters are read from the display memory (see table 3 ).
sda 525x semiconductor group 21 1998-04-08 er 24 ...er 0 = 1: row is interpreted as a blanked row er 24 ...er 0 = 0: row is received and displayed 6.2.6 display page addressing the display generator hardware generates a row/column address for the display memory. because there is a binary to row/column address translation between display generator and memory, the osd programmer has to take care of this. the relationship between row/column and binary address in memory is shown in table 4 . table 3 clear page bits row 25 /column: d7 d6 d5 d4 d3 d2 d1 d0 0er 7 er 6 er 5 er 4 er 3 er 2 er 1 er 0 1er 15 er 14 er 13 er 12 er 11 er 10 er 9 er 8 2er 23 er 22 er 21 er 20 er 19 er 18 er 17 er 16 3 0000000er 24 table 4 row/column to binary translation table c0 ... c31 c32 ... c39 row0 00 h ... 1f h 3f8 h ... 3ff h row1 20 h ... 3f h 3f0 h ... 3f7 h . . . . . . . . . . . . . . . . . . . . . row23 2e0 h ... 2ff h 340 h ... 347 h row24 300 h ... 31f h 338 h ... 33f h row25 320 h ... 337 h
sda 525x semiconductor group 22 1998-04-08 6.2.7 character generator the character generator includes the character and control code decoder, the ram interface and the rgb-, blan- and cor-signal generator. the display generator reads data from the display ram and calculates appropriate data which drives the rgb output pins. the pixel clock is generated by a start-stop-oscillator. the synchronization of display and pixel clock is done via external sandcastle or hs and vs signals. for 60 hz display the number of lines per character can be reduced to 9 or 8. in this case pixel information of line 10 or 9 plus 10 are rejected. with this mode combined with the variable vertical offset it is possible to generate ntsc displays with 25 rows. characters with a binary value < 32 are interpreted as control characters. for binary values 3 32 a rom character is selected through the addition of the character address, the language setting in sfr, the europe designation and the graphics control bits delivered from the control bit decoder. a total of 64 osd characters and 64 mosaic graphics characters are available. osd characters with addresses 80...sf h can be displayed together with 60 lower case characters because there is no memory overlapping with any other characters. osd characters with addresses 60...7f h can only be displayed if bit osd in sfr langc is set (see diagrams: physical address space and vertical address space). figures 6 - 13 shows the character rom contents. the control byte decoder analyses the serial attributes from the display memory and generates control clocks for the rgb logic and the character address decoder. the interpretation of control characters is corresponding to world standard teletext norm. table 5 shows the characters and the appearance on the screen. the rgb logic combines data from the character address decoder, control byte decoder and settings from the sfr registers and generates signal r, g, b, blan and cor. 6.2.8 on screen display (osd) a display page in the display memory can also be used for on screen displays. it should be recognized that all serial attributes of a normal text page are also valid for an osd display. therefore if double height is selected anywhere in a normal text page, row n and row n-1 (upper row) should be saved and overwritten by osd data in order to generate a correct display. switching back to text display is accomplished by rewriting the text data to the page. the same procedure is needed for the erase row bits in row 25. by means of enable box bits, transparent control bits and the serial attribute osd, the osd screen can be controlled fully independent of the normal text page. the serial osd-bit toggles the screen between normal display and osd.
sda 525x semiconductor group 23 1998-04-08 (1) reset state at begin of each row. (2) takes effect with control character. other control characters takes effect in the next character field. (3) two identical control characters are transmitted in sequence. the effect begins between the control characters. (4) can only be activated if sfr dmod.0 is set to 1, otherwise no influence. (5) toggle; takes effect with next character (on), takes effect with control character (off). table 5 serial control bytes b7, b6, b5, b4 0 1 b3, b2, b1, b0 0 alpha black mosaic black 1 alpha red mosaic red 2 alpha green mosaic green 3 alpha yellow mosaic yellow 4 alpha blue mosaic blue 5 alpha magenta mosaic magenta 6 alpha cyan mosaic cyan 7 alpha white (1) mosaic white 8 flash conceal (2) 9 steady (1,2) contiguous mosaic (1,2) a end box (1,3) separated mosaic (2) b start box (3) osd (5) c normal height (1,2) black background (2) d double height new background (2) e double width (4) hold mosaic (2) f double size (4) release mosaic (1)
sda 525x semiconductor group 24 1998-04-08 6.2.9 display special function registers the display generator includes 9 registers to select the different formats and functions. display horizontal delay register dhd display vertical delay register dvd display horizontal delay register dhd sfr-address c3 h default after reset: 00 h (msb) (lsb) hd.7 hd.6 hd.5 hd.4 hd.3 hd.2 hd.1 hd.0 hd.7 ... hd.0 variable negative horizontal display offset relative to positive edge of hs in pixel units. comments none display vertical delay register dvd sfr-address c4 h default after reset: 00 h (msb) (lsb) C C vd.5 vd.4 vd.3 vd.2 vd.1 vd.0 vd.5 ... vd.0 variable negative vertical display offset relative to positive edge of vs in hs units. comments none
sda 525x semiconductor group 25 1998-04-08 display transparent control register dtcr note: outside of a box means outside of a box opened by control code sequence 0b,0b and outside of an osd-box opened by control code 1b. inside a box means inside of a box opened by control code sequence 0b,0b or inside an osd-box opened by control code 1b. comments for further transparent modes see sfr dcrp. display transparent control register dtcr sfr-address c5 h default after reset: 00 h (msb) (lsb) cori coro icrp ibp trfi trfo trbi trbo trbo 1 = transparent background colors outside box and osd. trbi 1 = transparent background colors inside box or osd. trfo 1 = transparent foreground colors outside box and osd. trfi 1 = transparent foreground colors inside box or osd. ibp 1 = invert blanking polarity. blanking is active high. 0 = blanking is active low. icrp 1 = invert contrast reduction polarity. cor is active high. 0 = cor is active low. coro 1 = contrast reduction for background color outside box and outside osd. cori 1 = contrast reduction for background color inside box or inside osd.
sda 525x semiconductor group 26 1998-04-08 display mode register dmod note: this register is not readable. thus, do not use read-modify-write operations like anl, orl to modify this register. display feature double size and double width double size and double width are selectable via serial attributes. the control codes are 0e for double width and 0f for double size. now, there are 4 control codes available, to modify the character size: since double width and double size control codes should not be interpreted by a pure level 1 text-decoder, this size attributes have to be enabled by setting sfr-bit dsdw. double width and double size characters are accomplished by skipping every second character code after setting any of this following attributes where the remaining displayable characters are stretched horizontally and thus conceating the character. although every second character is hidden, these codes will take effect if they are control characters. display mode register dmod sfr-address d6 h default after reset: xxxx0000b (msb) (lsb) CCCC000 dsdw dsdw if set, displaying double size and double width characters is enabled if cleared, control codes 0e h and 0f h have no effect bit 1 to 3 have always to be written with 0 bit 4 to 7 not implemented, to be written with 0 control code name effect side effects 0c 0d 0e 0f normal size double height double width double size no stretching vertical character stretching horizontal character stretching horizontal and vertical stretching any activated stretching off horizontal stretching off vertical stretching off none
sda 525x semiconductor group 27 1998-04-08 display mode register 1 dmode1 display mode register 1 dmode1 sfr-address c6 h default after reset: 00 h (msb) (lsb) st_top st_dis con dh.1 dh.0 bd_24 bd_1_23 bd_0 bd_0 1 = box characters in row 0 are ignored. 0 = box characters in row 0 are displayed. bd_1_23 1 = box characters in row 1 - 23 are ignored. 0 = box characters in row 1 - 23 are displayed. bd_24 1 = box characters in status row are ignored. 0 = box characters in status row are allowed. dh.1 ... dh.0 00 = normal row display. 01 = rows 0 - 11 are displayed in double height. status row is displayed in normal height. 10 = rows 12 - 23 are displayed in double height. status row is displayed in normal height. 11 = not defined. con 1 = concealed characters are visible. 0 = concealed characters are not visible. st_dis 1 = status row is handled as blanked row. 0 = status row is displayed. st_top 1 = status row is displayed in row 0 of display. 0 = status row is displayed in row 24 of display. comments only boxes opened by the control code sequence 0b h , 0b h will be influenced, an osd-box (opened by control code 1b h ) will not be affected.
sda 525x semiconductor group 28 1998-04-08 display mode register 2 dmode2 display mode register 2 dmode2 sfr-address c7 h default after reset: 00 h (msb) (lsb) dtest.2 dtest.1 dtest.0 dchap.2 dchap.1 dchap.0 c10 c7 c7 1 = header is handled as erased row (suppress header). c10 1 = rows 1 - 23 are handled as erased rows (inhibit display). dchap.2..0 selects one of eight display chapters. dtest.0 not defined, must be set to 0. dtest.1 not defined, must be set to 0. dtest.2 not defined, must be set to 0. comments for 1-page-versions (sda 5251, sda 5252) the bits dchap.2..0 have to be set to 0.
sda 525x semiconductor group 29 1998-04-08 language control register langc language control register langc sfr-address c9 h default after reset: 00 h (msb) (lsb) osd_64 langc.6 langc.5 langc.4 langc.3 langc.2 langc.1 langc.0 langc.4... langc.0 language selection for text outside of an osd window. 00000 : german 01010 : english 01011 : scandinavian 01100 : italian 01101 : french 01110 : spanish 11001 : turkish 11010 : rumanian 11011 : hungarian 11100 : czechish 11101 : polish 11110 : serbian others : not defined langc.6... langc.5 00: west european special characters are addressable. 01: west european special characters are addressable (turkish). 10: east european special characters are addressable. 11: not defined. osd_64 1: 64 osd character mode on. if the serial attribute osd is set a total of 64 osd characters is available. the lower case g0 characters can not be used. 0: 32 osd character mode on. only osd characters in rom column 8 and 9 are available if serial attribute osd is set. outside an osd box all 64 osd characters are available (see figure 12 ). comments see diagrams x and y physical and vertical address spaces
sda 525x semiconductor group 30 1998-04-08 display cursor column position register dccp display cursor row position register dcrp display cursor column position register dccp sfr-address ca h default after reset: 00 h (msb) (lsb) C dc_en dccp.5 dccp.4 dccp.3 dccp.2 dccp.1 dccp.0 dc_en 1 = display cursor enable. 0 = display cursor disable. dccp.5...dccp.0 active cursor column position. dccp.5...0 = 0 d : column 1 on screen. bit 7 reserved, should be set to 0. comments none display cursor row position register dcrp sfr-address cb h default after reset: 00 h (msb) (lsb) trbos coros C dcrp.4 dcrp.3 dcrp.2 dcrp.1 dcrp.0 dcrp.4...dcrp.0 defines row of active cursor position. trbos 1 = the outer screen display area appears transparent 0 = the outer screen display area gets the background colour defined in register dtim coros 1 = contrast reduction outer screen bit 5 reserved, should be set to 0. comments bits trbos and coros thematically belong to the sfr dtcr
sda 525x semiconductor group 31 1998-04-08 display timing control register dtim display timing control register dtim sfr-address cc h default after reset: 00 h (msb) (lsb) bg_r bg_g bg_b eo_p30 eo_vs sandc lin9 lin8 lin8 lin9 sandc eo_vs eo_p30 1 = 8 line character mode (higher priority than lin9). 1 = 9 line character mode. 1 = horizontal and vertical synchronization accepts sandcastle pulse from pad hs/sc. 0 = horizontal and vertical synchronization accepts hs and vs pulses from pads hs/sc and vs respectively. 1 = the odd/even-signal evaluated from cvbs is enabled on pin vs. 0 = odd/even function is disabled. 1 = the odd/even-signal evaluated from cvbs is enabled on pin p3.0. 0 = odd/even function is disabled. bg_r bg_g bg_b bg_r bg_g bg_b bg_r bg_g bg_b black 0 0 0 yellow 1 1 0 red 1 0 0 violet 1 0 1 green 0 1 0 cyan 0 1 1 blue 0 0 1 white 1 1 1 outer screen background colour
sda 525x semiconductor group 32 1998-04-08 teletext-sync-interrupt-register ttxsir teletext-sync-interrupt- register ttxsir sfr-address c8 h default after reset: 00 h (msb) (lsb) C vsy hsy pclk dviren dvirst dhiren dhirst dhirst 1 = display horizontal sync interrupt request (set by positive edge of hs, reset by software). dhiren 1 = enable display horizontal sync interrupt requests. dvirst 1 = display vertical sync interrupt request (set by positive edge of vs, reset by software). dviren 1 = enable display vertical sync interrupt requests. pclk reflects state of internal pixel clock. hsy reflects state of hs-signal decoded by sc-decoder vsy reflects state of vs-signal decoded by sc-decoder (sandc=1). reflects state of vs-pin (sandc=0). bit 7 reserved, should be set to 0
sda 525x semiconductor group 33 1998-04-08 6.2.10 sandcastle decoder to fit the requirements of various applications the input circuit of the sandcastle decoder is programmable. both slicing levels ( v sch , v scl2 ) which are important for proper sc- decoder function can be varied in a range of about 0.9 v and in addition there is the possibility to increase the implemented hysteresis by 0.3 v typically. further noise reduction and spike rejection on pin sc is accomplished by using a digital filter following the input circuitry. see figure 41 on page 133 for further information on v sch and v scl2 . sandcastle control register sccon sandcastle control register sccon sfr-address ce h default after reset: 00 h (msb) (lsb) 0 scch.2 scch.1 scch.0 0 sccl.2 sccl.1 sccl.0 sccl1...0 00 = set v scl2 to lowest level (1.0 v typ.) 01 = increase v scl2 by 0.3 v (typ.) 10 = increase v scl2 by 0.6 v (typ.) 11 = increase v scl2 by 0.9 v (typ.) scl.2 0 = hysteresis v scl2 set to 0.3 v (typ.) 1 = increase hysteresis v scl2 by 0.6 v (typ.) scch1...0 00 = set v sch to lowest level 3.0 v (typ.) 01 = increase v sch by 0.3 v (typ.) 10 = increase v sch by 0.6 v (typ.) 11 = increase v sch by 0.9 v (typ.) scch.2 0 = hysteresis v sch set to 0.3 v (typ.) 1 = increase hysteresis v sch by 0.6 v attention bits 3 and 7 have to be set to 0.
sda 525x semiconductor group 34 1998-04-08 figure 6 g0 character set note: no = hardware mapped national option character 2/0 2/1 2/2 2/3 2/4 2/5 2/6 2/7 2/8 2/9 2/a 2/b 2/c 3/8 3/c 3/b 3/f 3/9 3/2 3/5 3/7 3/6 3/4 3/3 3/1 3/0 4/8 4/c 4/b 4/a 4/9 4/2 4/5 4/7 4/6 4/4 4/3 4/1 4/0 5/8 5/c 5/b 5/a 5/9 5/2 5/5 5/7 5/6 5/4 5/3 5/1 5/0 6/8 6/c 6/b 6/a 6/9 6/2 6/5 6/7 6/6 6/4 6/3 6/1 6/0 7/c 7/0 7/2 7/1 7/3 7/4 7/5 7/6 7/7 7/8 7/9 7/a 7/b ued08127 7/d 6/d 5/d 4/d 3/d 2/d 2/e 3/e 4/e 5/e 6/e 7/e 2/f 3/f 4/f 5/f 6/f 7/f no no no no no no no no no no no no no
sda 525x semiconductor group 35 1998-04-08 figure 7 character set west europe a/0 a/1 a/2 a/3 a/4 a/5 a/6 a/7 a/8 a/9 a/a a/b a/c b/8 b/c b/b b/a b/9 b/2 b/5 b/7 b/6 b/4 b/3 b/1 b/0 c/8 c/c c/b c/a c/9 c/2 c/5 c/7 c/6 c/4 c/3 c/1 c/0 d/8 d/c d/b d/a d/9 d/2 d/5 d/7 d/6 d/4 d/3 d/1 d/0 e/8 e/c e/b e/a e/9 e/2 e/5 e/7 e/6 e/4 e/3 e/1 e/0 f/c f/0 f/2 f/1 f/3 f/4 f/5 f/6 f/7 f/8 f/9 f/a f/b ued08128 f/d e/d d/d c/d b/d a/d a/e b/e c/e d/e e/e f/e a/f b/f c/f d/f e/f f/f
sda 525x semiconductor group 36 1998-04-08 figure 8 character set west europe (turkish) a/0 a/1 a/2 a/3 a/4 a/5 a/6 a/7 a/8 a/9 a/a a/b a/c b/8 b/c b/b b/a b/9 b/2 b/5 b/7 b/6 b/4 b/3 b/1 b/0 c/8 c/c c/b c/a c/9 c/2 c/5 c/7 c/6 c/4 c/3 c/1 c/0 d/8 d/c d/b d/a d/9 d/2 d/5 d/7 d/6 d/4 d/3 d/1 d/0 e/8 e/c e/b e/a e/9 e/2 e/5 e/7 e/6 e/4 e/3 e/1 e/0 f/c f/0 f/2 f/1 f/3 f/4 f/5 f/6 f/7 f/8 f/9 f/a f/b ued08129 f/d e/d d/d c/d b/d a/d a/e b/e c/e d/e e/e f/e a/f b/f c/f d/f e/f f/f
sda 525x semiconductor group 37 1998-04-08 figure 9 character set east europe ued08130 a/f a/e a/d a/c a/b a/a a/9 a/8 a/7 a/3 a/6 a/5 a/4 a/2 a/1 a/0 b/f b/e b/d b/a b/b b/c b/7 b/9 b/8 b/3 b/4 b/6 b/5 b/0 b/1 b/2 c/f c/e c/d c/c c/a c/b c/9 c/7 c/8 c/3 c/6 c/5 c/4 c/2 c/0 c/1 d/f d/e d/d d/0 d/1 d/3 d/4 d/6 d/7 d/5 d/2 d/9 d/a d/b d/c d/8 e/f e/e e/d e/c e/a e/b e/9 e/7 e/8 e/3 e/6 e/5 e/4 e/2 e/0 e/1 f/f f/e f/d f/b f/a f/c f/9 f/8 f/7 f/3 f/6 f/5 f/4 f/1 f/2 f/0
sda 525x semiconductor group 38 1998-04-08 figure 10 national option characters i 2/3 2/4 4/0 5/b 5/c 5/d 5/e 5/f 6/0 7/b 7/c 7/d 7/e 6/0 7/e 7/d 7/c 7/b 4/0 5/d 5/f 5/e 5/c 5/b 2/4 2/3 6/0 7/e 7/d 7/c 7/b 4/0 5/d 5/f 5/e 5/c 5/b 2/4 2/3 6/0 7/e 7/d 7/c 7/b 4/0 5/d 5/f 5/e 5/c 5/b 2/4 2/3 6/0 7/e 7/d 7/c 7/b 4/0 5/d 5/f 5/e 5/c 5/b 2/4 2/3 german english scandinavian italian french ued08131 7/e 7/c 7/d 7/b 5/f 6/0 spanish 5/b 5/e 5/d 5/c 4/0 2/3 2/4
sda 525x semiconductor group 39 1998-04-08 figure 11 national option characters ii ued08132 turkish polish czechian romanian serbian 7/e 7/d 7/c 7/b 6/0 5/f 5/b 5/e 5/d 5/c 4/0 2/4 2/3 7/c 7/d 7/e 5/f 7/b 6/0 5/b 5/c 5/e 5/d 2/3 2/4 4/0 7/e 7/c 7/d 7/b 5/f 6/0 5/b 5/e 5/d 5/c 4/0 2/3 2/4 2/3 2/4 5/b 5/c 5/e 5/f 5/d 4/0 7/b 7/c 7/d 7/e 6/0 7/e 7/c 7/d 7/b 5/f 6/0 5/b 5/e 5/d 5/c 4/0 2/3 2/4
sda 525x semiconductor group 40 1998-04-08 figure 12 osd characters set (these characters are customized and thus left blank on this page) note: characters ... to ... can only be used inside an osd box. ued08133 6/f 6/e 6/d 6/c 6/a 6/b 6/9 6/7 6/8 6/3 6/6 6/5 6/4 6/2 6/0 6/1 7/f 7/e 7/d 7/b 7/a 7/c 7/9 7/8 7/7 7/3 7/6 7/5 7/4 7/1 7/2 7/0 9/e 9/f 9/c 9/b 9/d 9/a 9/7 9/8 9/9 9/3 9/4 9/5 9/6 9/0 9/2 9/1 8/f 8/e 8/c 8/d 8/b 8/a 8/9 8/7 8/8 8/3 8/5 8/6 8/4 8/2 8/1 8/0
sda 525x semiconductor group 41 1998-04-08 figure 13 graphics character set ued08134 6/f 6/e 6/d 6/c 6/a 6/b 6/9 6/7 6/8 6/3 6/6 6/5 6/4 6/2 6/0 6/1 7/f 7/e 7/d 7/b 7/a 7/c 7/9 7/8 7/7 7/3 7/6 7/5 7/4 7/1 7/2 7/0 2/f 2/e 2/d 2/c 2/b 2/a 2/9 2/8 2/7 2/3 2/6 2/5 2/4 2/2 2/1 2/0 3/f 3/e 3/d 3/f 3/b 3/c 3/7 3/9 3/8 3/3 3/4 3/6 3/5 3/0 3/1 3/2
sda 525x semiconductor group 42 1998-04-08 6.3 microcontroller 6.3.1 architecture the cpu manipulates operands in two memory spaces: the program memory space, and the data memory space. the program memory address space is provided to accommodate relocatable code. the data memory address space is divided into the 256-byte internal data ram, xram (extended data memory, accessible with movx-instructions) and the 128-byte special function register (sfr) address spaces. four register banks (each bank has eight registers), 128 addressable bits, and the stack reside in the internal data ram. the stack depth is limited only by the available internal data ram. its location is determined by the 8-bit stack pointer. all registers except the program counter and the four 8-register banks reside in the special function register address space. these memory mapped registers include arithmetic registers, pointers, i/o-ports, registers for the interrupt system, timers, pulse width modulator and serial channel. many locations in the sfr-address space are addressable as bits. note that reading from unused locations within data memory will yield undefined data. conditional branches are performed relative to the 16 bit program counter. the register- indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. sixteen-bit jumps and calls permit branching to any location in the memory address space. the processor as five methods for addressing source operands: register, direct, register- indirect, immediate, and base-register plus index-register indirect addressing. the first three methods can be used for addressing destination operands. most instructions have a destination, source field that specifies the data type, addressing methods and operands involved. for operations other than moves, the destination operand is also a source operand. registers in the four 8-register banks can be accessed through register, direct, or register-indirect addressing; the lower 128 bytes of internal data ram through direct or register-indirect addressing, the upper 128 bytes of internal data ram through register- indirect addressing; and the special function registers through direct addressing. look- up tables resident in program memory can be accessed through base-register plus index-register indirect addressing.
sda 525x semiconductor group 43 1998-04-08 6.3.1.1 cpu-hardware instruction decoder each program instruction is decoded by the instruction decoder. this unit generates the internal signals that control the functions of each unit within the cpu-section. these signals control the sources and destination of data, as well as the function of the arithmetic/logic unit (alu). program control section the program control section controls the sequence in which the instructions stored in program memory are executed. the conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution. the 16-bit program counter holds the address of the instruction to be executed. it is manipulated with the control transfer instructions listed in chapter instruction set on page 116 . internal data ram the internal data ram provides a 256-byte scratch pad memory, which includes four register banks and 128 direct addressable software flags. each register bank contains registers r0 C r7. the addressable flags are located in the 16-byte locations starting at byte address 32 and ending with byte location 47 of the ram-address space. in addition to this standard internal data ram the processor contains an extended internal ram. it can be considered as a part of an external data memory. it is referenced by movx-instructions (movx a, @dptr), the memory map is shown in figure 21 . arithmetic/logic unit (alu) the arithmetic section of the processor performs many data manipulation functions and includes the arithmetic/logic unit (alu) and the a, b and psw-registers. the alu accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. the alu performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, bcd-decimal-add-adjust and compare, and the logic operations of and, or, exclusive-or, complement and rotate (right, left, or nibble swap). the a-register is the accumulator, the b-register is dedicated during multiply and divide and serves as both a source and a destination. during all other operations the b-register is simply another location of the special function register space and may be used for any purpose.
sda 525x semiconductor group 44 1998-04-08 boolean processor the boolean processor is an integral part of the processor architecture. it is an independent bit processor with its own instruction set, its own accumulator (the carry flag) and its own bit- addressable ram and i/o. the bit manipulation instructions allow the direct addressing of 128 bits within the internal data ram and several bits within the special function registers. the special function registers which have addresses exactly divisible by eight contain directly addressable bits. the boolean processor can perform, on any addressable bit, the bit operations of set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set then-clear and move to/from carry. between any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical and or logical or with the result returned to the carry flag. program status word register (psw) the psw-flags record processor status information and control the operation of the processor. the carry (cy), auxiliary carry (ac), two user flags (f0 and f1), register bank select (rs0 and rs1), overflow (ov) and parity (p) flags reside in the program status word register. these flags are bit-memory-mapped within the byte-memory-mapped psw. the cy, ac, and ov flags generally reflect the status of the latest arithmetic operations. the cy-flag is also the boolean accumulator for bit operations. the p-flag always reflects the parity of the a-register. f0 and f1 are general purpose flags which are pushed onto the stack as part of a psw-save. the two register bank select bits (rs1 and rs0) determine which one of the four register banks is selected as follows: program status word psw table 6 program status word register rs1 rs0 register bank register location 0 0 1 1 0 1 0 1 0 1 2 3 00 h C 07 h 08 h C 0f h 10 h C 17 h 18 h C 1f h program status word psw sfr-address d0 h (msb) (lsb) cy ac f0 rs1 rs0 ov f1 p
sda 525x semiconductor group 45 1998-04-08 stack pointer (sp) the 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. this is also the address of the next byte that will be popped. the sp is incremented during a push. sp can be read or written to under software control. the stack may be located anywhere within the internal data ram address space and may be as large as 256 bytes. data pointer register (dptr) the 16-bit data pointer register dptr is the concatenation of registers dph (high- order byte) and dpl (low-order byte). the dptr is used in register-indirect addressing to move program memory constants and to access the extended data memory. dptr may be manipulated as one 16-bit register or as two independent 8-bit registers dpl and dph. eight data pointer registers are available, the active one is selected by a special function register (dpsel). port 0, port 1, port 2, port 3, port 4 the five ports provide 26 i/o-lines and 5 input-lines to interface to the external world. all five ports are both byte and bit addressable. port 0 is used for binary l/o and as clock and data line of a software driven i 2 c bus. port 1 provides eight pwm- output channels as alternate functions while port 2.0 - 2.3 are digital or analog inputs. port 3 contains special control signals. port 4 will usually be selected as memory extension interface (rom-less version only). interrupt logic controlled by three special function registers (ie, ip0 and ip1) the interrupt logic provides several interrupt vectors. each of them may be assigned to high or low priority (see chapter interrupt system on page 62 ). timer/counter 0/1 two general purpose 16-bit timers/counters are controlled by the special function registers tmod and tcon (see chapter general purpose timers/counters on page 80 ). serial interface a full duplex serial interface is provided where one of three operation modes may be selected. the serial interface is controlled by two special function registers (scon, sbuf) as described in chapter serial interface on page 91 .
sda 525x semiconductor group 46 1998-04-08 watchdog timer for software- and hardware security, a watchdog timer is supplied, which resets the processor, if not cleared by software within a maximum time period. pulse width modulation unit up to six lines of port 1 may be used as 8-bit pwm-outputs and two lines of port 1 may be used as 14-bit pwm-output. the pwm-logic is controlled by registers pwcomp0 7, pwcl, pwch, pwme, pwext6, pwext7 (see chapter pulse width modulation unit (pwm) on page 106 ). capture compare timer for easy decoding of infrared remote control signals, a dedicated timer is available (see chapter capture compare timer on page 90 ). 6.3.1.2 cpu-timing timing generation is completely self-contained, except for the frequency reference which can be a crystal or external clock source. the on-board oscillator is a parallel anti- resonant circuit. there is a divide-by-6 internal timing which leads to a minimum instruction cycle of 0.33 m s with an 18-mhz crystal. the xtal2-pin is the output of a high-gain amplifier, while xtal1 is its input. a crystal connected between xtal1 and xtal2 provides the feedback and phase shift required for oscillation. a machine cycle consists of 6 oscillator periods (software selectable). most instructions execute in one cycle. mul (multiply) and div (divide) are the only instructions that take more than two cycles to complete. they take four cycles. to reduce the power consumption, the internal clock frequency can be divided by two, which slows down the processor operations. this slow down mode is entered by setting sfr-bit cdc in register afr. note: all timing values and diagrams in this specification refer to an inactivated clock divider (cdc = 0). note: slow down mode should only be used if teletext reception and the display are disabled. otherwise processing of the incoming text data might be incomplete and the display structure will be corrupted.
sda 525x semiconductor group 47 1998-04-08 figure 14 cpu-timing note: for cdc see chapter advanced function register on page 115 . 6.3.1.3 addressing modes there are five general addressing modes operating on bytes. one of these five addressing modes, however, operates on both bytes and bits: C register C direct (both bytes and bits) C register indirect C immediate C base-register plus index-register indirect the following section summarizes, which memory spaces may be accessed by each of the addressing modes: register addressing r0 C r7 acc, b, cy (bit), dptr direct addressing ram (low part) special function registers register-indirect addressing ram (@r1, @r0, sp) immediate addressing program memory base-register plus index-register indirect addressing program memory (@dptr + a, @pc + a) ues05470 cdc = 0 cdc = 1 chip clock 2 osc internal instruction cycles machine cycles, . . . . 6
sda 525x semiconductor group 48 1998-04-08 register addressing register addressing accesses the eight working registers (r0 C r7) of the selected register bank. the psw-register flags rs1 and rs0 determine which register bank is enabled. the least significant three bits of the instruction opcode indicate which register is to be used. acc, b, dptr and cy, the boolean processor accumulator, can also be addressed as registers. direct addressing direct byte addressing specifies an on-chip ram-location (only low part) or a special function register. direct addressing is the only method of accessing the special function registers. an additional byte is appended to the instruction opcode to provide the memory location address. the highest-order bit of this byte selects one of two groups of addresses: values between 0 and 127 (00 h C 7f h ) access internal ram-locations, while values between 128 and 255 (80 h C 0ff h ) access one of the special function registers. register-indirect addressing register-indirect addressing uses the contents of either r0 or r1 (in the selected register bank) as a pointer to locations in the 256 bytes of internal ram. note that the special function registers are not accessable by this method. execution of push- and pop-instructions also use register-indirect addressing. the stack pointer may reside anywhere in internal ram. immediate addressing immediate addressing allows constants to be part of the opcode instruction in program memory. an additional byte is appended to the instruction to hold the source variable. in the assembly language and instruction set, a number sign (#) precedes the value to be used, which may refer to a constant, an expression, or a symbolic name. base-register plus index register-indirect addressing base-register plus index register-indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (dptr or pc) and index register, acc. this mode facilitates accessing to look-up-table resident in program memory.
sda 525x semiconductor group 49 1998-04-08 6.3.2 memory organization the processor memory is organized into two address spaces. the memory spaces are: C program memory address space C 256 byte plus 128-byte internal data memory address space C extended internal data memory (xram) for storing teletext and display data. a 16-bit program counter and a dedicated banking logic provide the processor with its 512-kbyte addressing capabilities (for rom-less versions, up to 19 address lines are available). the program counter allows the user to execute calls and branches to any location within the program memory space. there are no instructions that permit program execution to move from the program memory space to any of the data memory space. 6.3.2.1 program memory certain locations in program memory are reserved for specific programs. locations 0000 through 0002 are reserved for the initialization program. following reset, the cpu always begins execution at location 0000. locations 0003 through 0051 are reserved for the seven interrupt-request service programs as indicated in table 7 . depending on the selected type, the user can access a part of the internal/external rom for the application software. please note that another part of the program memory is reserved for the ttx firmware. table 7 source address external interrupt 0 timer 0 overflow external interrupt 1 timer 1 overflow serial interface teletext sync signals analog digital converter 03 (03 h ) 11 (0b h ) 19 (13 h ) 27 (1b h ) 35 (23 h ) 43 (2b h ) 51 (33 h ) table 8 type available user rom space sda 5250 sda 5251 sda 5252 sda 5254 sda 5255 480 kbyte externally 8 kbyte internally 16 kbyte internally 16 kbyte internally 24 kbyte internally
sda 525x semiconductor group 50 1998-04-08 memory extension (romless version only) the processor is prepared to extend its external program memory space up to 512 kbytes ( figure 15 and 16 ). for easy handling of existing software and assemblers this space is split into 8 banks of 64 kbytes each. the extension concept, based on the standard 64 k addressing ability, is provided for high effective and easy memory access with minimum software overhead. there is also no need caring about bank organization during subroutine processing or interrupts. this is done through address bits a16 C 18, which are controlled by a special internal circuitry, performing a delayed banking. the operations to the extended memory spaces are controlled by two additional special function registers called mex1 and mex2 ( figure 17 ). the address bits a17 and a18 are implemented at port 4. programs, using only 128-kbytes program memory space, may switch the address function off by setting bits nb, ib and bits mb to 1 followed by a ljmp. then port 4 will work properly in port mode. whenever full address mode is desired, port 4 bits have to be kept on 1 ( table 9 ). after reset all cb are 0 and p4 latches are set to 1, resulting a 0 at the port 4 pins. banking of program memory after reset the bits for current bank (cb) and next bank (nb) are set to zero. this way the processor starts the same as any 8051 controller at address 00000 h . whenever a jump to another bank is required, the software has to change the bits nb16 C 18 for initializing the bank exchange (bits cb16 C 18 are read only). after operating the next ljmp instruction the nb16 C 18 bits (next bank) are copied to cb16 C 18 (current bank) and will appear at a16 C 18. only ljmp will do this. figure 15 connecting external program memory ues05663 p4 p3 p2 p1 p0 sda 5250 a psen d a d eprom oe alternative connections
sda 525x semiconductor group 51 1998-04-08 figure 16 bank organization figure 17 register bits mex1 / mex2 uec04716 bank 0 65535 131071 1 2 196607 3 262143 4 327679 5 393215 6 458751 524287 7 0000 65536 131072 196608 262144 327680 393216 458752 mex1 (94 h ): bank control mex2 (95 h ): mode control cb = current bank read only; cbx = ax nb = next bank r/w mm = memory mode r/w; 1 = use mb mb = memory bank r/w sf = stack full read only; 1 = full ib = interrupt bank r/w 76543210 mm mb18 mb17 mb16 sf ib18 ib17 ib16 76543210 C cb18 cb17 cb16 C nb18 nb17 nb16
sda 525x semiconductor group 52 1998-04-08 movc-handling movc-instructions may operate in two different modes, that are selected by bit mm in mex2. on mm = 0 movc will access the current bank. on mm = 1 the bits mb16 C 18 will appear at a16 C a18 during movc. figure 18 pc and dptr on different banks calls and interrupts for flexible use of call and interrupts the control logic holds an own 32 levels-six-bit- stack. whenever a lcall or acall occurs, cb16 C 18 and nb16 C 18 (mex1) is copied to this stack and the memory extension stackpointer is incremented. then nb16 C 18 is copied to cb16 C 18. leaving subroutines through ret or reti decrements the stack pointer and reads the old nb and cb contents from the stack. all six bits are required for saving to prevent conflicts on interrupt events. one additional feature simplifies the handling of interrupts: on occurrence the bits ib16 C 18 within mex2 are copied to cb16 C 18 and nb16 C 18 after pushing their old contents on the stack. this way programmers can place their isr (interrupt service routine) on specific banks. after reset mm, mb16 C 18 and ib16 C 18 are set to zero. table 9 port 4 configuration cb p4 latch p4 out comment 0 00x 0 1 0 address 1 00p4 1 1 1 addr / p4 uec04717 mm=1, mb 16-17 =3, cb 16-17 =2 bank 2 bank 3 dptr pc
sda 525x semiconductor group 53 1998-04-08 in order to prevent loss of program control during deep subroutine nesting a warning bit sf (stack full) is set in mex2 whenever a memory extension stack depth overflow is imminent. for example figure 19 shows the data flows at the memory extension stack during a lcall. all three bits of nb are copied to the position cb and nb of the next higher stack level (now the current mex1) while the last cb and nb are held on the stack. returning from subroutine through ret the memory extension stack pointer decrements and cb and nb of mex1 has the same contents as before lcall. figure 19 processing lcall (same as acall) examples the standard sequence jumping from one bank to another is simply preceding a mov mex1,#- instruction to an ljmp / lcall as shown in figure 19 . to operate programs up to 512 kbytes with standard assemblers or from c the program can be split into sections, modules or files, that will each run in their own bank. referencing banks to each other (jumps, calls, data moves) may be done by a simple preprocessing of the source programs or object files. users, going to program a 512-kbyte eprom in assembler, may proceed like this: 1. build up to eight assembler source files (max. 64 k), inter bank operations will refer to dummy labels. 2. do assembler runs on each block and generate label lists. 3. preprocessing: substitute the inter bank labels in the source files with absolute 64 k addresses. 4. second and final assembler runs on each block, generate hex files. 5. append the hex files in right order. 6. program an eprom. uec04718 010 110 mex1 cb nb before 110 010 after nb cb mex1 110 010 'lcall' 110 110 mex1: cb 18,17,16 18,17,16 nb
sda 525x semiconductor group 54 1998-04-08 more comfortable programming, e. g. based on c-programs, require similar processing of the source programs or object files with respect to special considerations of the compiler. figure 20 shows an assembler program run, performing the following actions: 1. start at bank 0 at 00000. 2. set isr-page to bank 2. 3. jump to bank 1 at address 25. 4. being interrupted to bank 2 isr. 5. call a subprogram at bank 2 address 43. 6. after return read data from bank 2. figure 20 program example uec04719 0040: prgm0: mov mex2,#02 ;prepare jumping ;from ;bank 0 to bank 1 mov mex1,#1 ljmp 25 ;'25' is a substitution of primary labels transformed to an absolute address at bank 2 0043: 0046: ;set isr bank = bank 2 org 40 bank 0 bank 1 org 25 0025: 0040: 0080: 0150: 0153: 0156: prgm1: mov... ;prepare ;calling prgm2 ;on bank 2 mov mex1,#2 lcall 43 ;fetch data from bank 2 ;(and update isr-bank mov mex2,#0a2 mov dptr,#100 movc a, @dptr pointer) org 13 bank 2 0013: ;isr on ;bank 2 reti org 43 prgm2: ;execute prgm2 ret org 100 byte 44 0043: 0060: 0100: interrupt to akku h h
sda 525x semiconductor group 55 1998-04-08 6.3.2.2 internal data ram the internal data memory is divided into four blocks: the lower 128 byte of ram, the upper 128 byte of ram, the 128-byte special function register (sfr) area and the up to 10 kbyte additional ram ( figure 21 ). because the upper ram-area and the sfr- area share the same address locations, they are accessed through different addressing modes. the internal data ram-address space is 0 to 255. four banks of eight registers each occupy locations 0 through 31. only one of these banks may be enabled at a time through a two-bit field in the psw. in addition, 128-bit locations of the on-chip ram are accessible through direct addressing. these bits reside in internal data ram at byte locations 32 through 47, as shown in table 11 . the lower 128 bytes of internal data ram can be accessed through direct or register-indirect addressing, the upper 128 bytes of internal data ram through register- indirect addressing and the special function registers through direct addressing.the stack can be located anywhere in the internal data ram-address space. the stack depth is limited only by the available internal data ram, thanks to an 8-bit relocatable stack pointer. the stack is used for storing the program counter during subroutine calls and may also be used for passing parameters. any byte of internal data ram or special function registers accessible through direct addressing can be pushed/popped. an additional on-chip ram-space called xram extends the internal ram-capacity. the up to 10 kbytes of xram are accessed by movx @dptr. xram is located in the upper area of the address space. 1 kbyte of the xram, called vbi buffer, is reserved for storing teletext data and another up to 8 kbyte of the xram, called display chapters, are reserved for storing up to 8 display chapters (see figure 21 ). unused memory area of the vbi buffer and the display chapters can be used by the controller as general ram space. : (1) sda 5251, sda 5252 c000 - c3ff only (2) sda 5250, sda 5254 and sda 5255 only table 10 xram address space function byte address (hex.) vbi buffer f400 - f7ff display chapter 0 - 7 c000 - dfff (1) cpu xram f800 - fbff (2)
sda 525x semiconductor group 56 1998-04-08 6.3.2.3 special function registers the special function register address space resides between addresses 128 and 255. all registers except the program counter and the four banks of eight working registers reside here. memory mapping the special function registers allows them to be accessed as easily as the internal ram. as such, they can be operated on by most instructions. a complete list of the special function registers is given in table 13 . in addition, many bit locations within the special function register address space can be accessed using direct addressing. these direct addressable bits are located at byte addresses divisible by eight as shown in table 12 .
sda 525x semiconductor group 57 1998-04-08 figure 21 internal data memory address space sda 5250, sda 5254 and sda 5255 only additional internal data ued05467 special function registers registers 127 48 47 120 127 7 0 32 31 24 16 0 8 255 128 255 128 internal data ram addressable bits in sfrs addressable bits in ram (128 bits) r7 r0 bank 64511 internal data ram 3 2 bank r0 r7 1 bank r0 r7 0 bank r0 r7 ram (xram) 63487 63488 controller work space buffer vbi 62464 57343 56320 56319 55296 55295 54272 54271 53248 53247 52224 52223 51200 51199 50176 50175 0 chapter display 49152 display chapter 1 display chapter 2 display chapter 3 display chapter 4 display chapter 5 display chapter 6 display chapter 7
sda 525x semiconductor group 58 1998-04-08 table 11 internal ram-bit addresses ram byte (msb) (lsb) 256 ff h 47 7f 7e 7d 7c 7b 7a 79 78 2f h 46 77 76 75 74 73 72 71 70 2e h 45 6f 6e 6d 6c 6b 6a 69 68 2d h 44 67 66 65 64 63 62 61 60 2c h 43 5f 5e 5d 5c 5b 5a 59 58 2b h 42 57 56 55 54 53 52 51 50 2a h 41 4f 4e 4d 4c 4b 4a 49 48 29 h 40 47 46 45 44 43 42 41 40 28 h 39 3f 3e 3d 3c 3b 3a 39 38 27 h 38 37 36 35 34 33 32 31 30 26 h 37 2f 2e 2d 2c 2b 2a 29 28 25 h 36 27 26 25 24 23 22 21 20 24 h 35 1f 1e 1d 1c 1b 1a 19 18 23 h 34 17 16 15 14 13 12 11 10 22 h 33 0f 0e 0d 0c 0b 0a 09 08 21 h 32 07 06 05 04 03 02 01 00 20 h 31 24 bank 3 1f h 18 h 23 16 bank 2 17 h 10 h 15 8 bank 1 0f h 08 h 7 0 bank 0 07 h 00 h ? ?
sda 525x semiconductor group 59 1998-04-08 table 12 special function register bit address space direct byte address hardware register symbol bit address f8 h ff fe fd fc fb fa f9 f8 pwme f0 h f7 f6 f5 f4 f3 f2 f1 f0 b e8 h CCCCCCe9e8p4 e0 h e7 e6 e5 e4 e3 e2 e1 e0 acc d8 h df de dd dc db C d9 d8 adcon d0 h d7 d6 d5 d4 d3 d2 d1 d0 psw c8 h C ce cd cc cb ca c9 c8 ttxsir c0 h c7 c6 c5 c4 c3 c2 c1 c0 acqsir b8 h CCCCCCCC b0 h b7 b6 b5 b4 b3 b2 b1 b0 p3 a8 h af ae ad ac ab aa a9 a8 ie a0 h CCCCa3a2a1a0p2 98 h 9f 9e 9d 9c 9b 9a 99 98 scon 90 h 97 96 95 94 93 92 91 90 p1 88 h 8f 8e 8d 8c 8b 8a 89 88 tcon 80 h 87 86 85 84 83 82 81 80 p0
sda 525x semiconductor group 60 1998-04-08 table 13 special function register overview special function register description symbolic name address location (hex.) address location (dec.) bit address msb lsb (hex.) initial value after reset (hex./bin.) arithmetic registers accumulator b-register program status word acc, a b psw e0 f0 d0 224 240 208 e7 - e0 f7 - f0 d7 - d0 00 00 00 system control registers stack pointer data pointer (high byte) data pointer (low byte) data pointer select power control sp dph dpl dpsel pcon 81 83 82 a2 87 129 131 130 162 135 C C C C 07 00 00 xxxxx000 000xxx00 i/o-port registers port 0 port 1 port 2 port 3 port 4 p0 p1 p2 p3 p4 80 90 a0 b0 e8 128 144 160 176 232 87 - 80 97 - 90 a3 - a0 b7 - b0 e9 - e8 ff ff ff ff xxxxxx00 interrupt control registers interrupt enable flags interrupt priority flags interrupt priority flags interrupt control ie ip0 ip1 ircon a8 a9 aa a8 168 169 170 171 af - a8 C C C 00 00 00 xxxx0101 timer 0/1 registers timer 0/1 mode register timer 0/1 control register timer 1 (high byte) timer 0 (high byte) timer 1 (low byte) timer 0 (low byte) tmod tcon th1 th0 tl1 tl0 89 88 8d 8c 8b 8a 137 136 141 140 139 138 C 8f - 88 C C C C 00 00 00 00 00 00 watchdog timer registers watchdog control register watchdog reload register watchdog low byte watchdog high byte wdcon wdtrel wdtl wdth a7 86 84 85 167 134 132 133 C C C C 00 00 00 00 capture compare timer registers rell relh capl caph irtcon e1 e2 e3 e4 e5 225 226 227 228 229 C C C C C xx xx xx xx 00
sda 525x semiconductor group 61 1998-04-08 analog digital converter adc-control register adc-data register adc-start register adcon addat dapr d8 d9 da 216 217 218 df - d8 C C 00 00 xx pulse width modulator registers enable register counter register (low byte) counter register (high byte) compare register 0 compare register 1 compare register 2 compare register 3 compare register 4 compare register 5 pwm 14 compare reg. 0 pwm 14 extension reg. 0 pwm 14 compare reg. 1 pwm 14 extension reg. 1 pwme pwcl pwch pwcomp0 pwcomp1 pwcomp2 pwcomp3 pwcomp4 pwcomp5 pwcomp6 pwext6 pwcomp7 pwext7 f8 f7 f9 f1 f2 f3 f4 f5 f6 fb fa fd fc 248 247 249 241 242 243 244 245 246 251 250 253 252 ff - f8 C C C C C C C C C C C C 00 00 00 ff ff ff ff ff ff ff ff ff ff serial interface registers serial control register serial data register scon sbuf 98 99 144 145 9f - 98 C 00 xx advanced function register afr a6 166 C 00xxxxxx slicer control registers acq. sync interrupt register acquisition mode register 1 acquisition mode register 2 acqsir acqms_1 acqms_2 c0 c1 c2 192 193 194 c7 - c0 C C 00 00 00 table 13 special function register overview (contd) special function register description symbolic name address location (hex.) address location (dec.) bit address msb lsb (hex.) initial value after reset (hex./bin.)
sda 525x semiconductor group 62 1998-04-08 6.3.3 interrupt system external events and the real-time on-chip peripherals require cpu-service asynchronous to the execution of any particular section of code. to couple the asynchronous activities of these functions to normal program execution, a sophisticated multiple-source, four-priority-level, nested interrupt system is provided. interrupt response delay ranges from 0,89 m s to 2.33 m s when using an 18-mhz clock (see chapter advanced function register on page 115 ). 6.3.3.1 interrupt sources the processor acknowledges interrupt requests from seven sources: two from external sources via the int0 and int1 pins, one from each of the two internal counters, one from the serial i/o-port, one from teletext sync signals and one from the analog digital converter. each of the seven sources can be assigned to either of four priority levels and can be independently enabled and disabled. additionally, all enabled sources can be globally disabled or enabled. interrupts result in a transfer of control to a new program location. each interrupt vectors to a separate location in program memory for its service program. the program servicing the request begins at this address. the starting address (interrupt vector) of the interrupt service program for each interrupt source is shown in the table 14 . display control registers horizontal delay vertical delay transparent control mode 1 register mode 2 register sync interrupt request reg. language control cursor column position cursor row position display timing control sandcastle control display mode dhd dvd dtcr dmode1 dmode2 ttxsir langc dccp dcrp dtim sccon dmod c3 c4 c5 c6 c7 c8 c9 ca cb cc ce d6 195 196 197 198 199 200 201 202 203 204 206 214 C C C C C cf - c8 C C C C C C 00 00 00 00 00 00 00 00 00 00 00 x0 table 13 special function register overview (contd) special function register description symbolic name address location (hex.) address location (dec.) bit address msb lsb (hex.) initial value after reset (hex./bin.)
sda 525x semiconductor group 63 1998-04-08 6.3.4 interrupt control the information flags, which control the entire interrupt system, are stored in following special function registers: ie interrupt enable register a8 h ip0 interrupt priority register 1 a9 h ip1 interrupt priority register 2 aa h ircon interrupt control ab h tcon timer/counter control register 88 h scon serial control register 98 h ttxsir sync interrupt request register c8 h acqsir acquisition sync interrupt register c0 h adcon adc-control register d8 h the interrupt system is shown diagrammatically in figure 23 . a source requests an interrupt by setting its associated interrupt request flag in the tcon, scon, ttxsir, acqsir or adcon- register, as described in detail in table 15 . table 14 interrupt source starting address external request 0 internal timer/counter 0 external request 1 internal timer/counter 1 serial interface teletext sync signals analog digital converter 03 (03 h ) 11 (0b h ) 19 (13 h ) 27 (1b h ) 35 (23 h ) 43 (2b h ) 51 (33 h )
sda 525x semiconductor group 64 1998-04-08 the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter register, except for timer 0 in mode 3. the serial interface interrupt (receive or transmit) is generated when flag ri or ti is set. ri or ti will be set, when a byte has been received or transmitted over the serial port. for details see chapter more about mode 0 on page 95 , chapter more about mode 1 on page 95 and chapter more about modes 2 and 3 on page 96 . the teletext sync signal interrupt is generated by setting and enabling at least one of six possible signal sources: two signals from the display clock system (v and h) and 4 signals from the acquisition clock system (start of even field, start of acq- line 24 in each field, v and h) as shown in figure 22 . the teletext sync signal interrupt is synchronous to the respective acquisition or display clock system. thus clock synchronous software timers can be realized. the analog digital converter interrupt is generated on completion of the analog digital conversion. within the ie-register there are eight addressable flags. seven flags enable/disable the seven interrupt sources when set/cleared. setting/clearing the eighth flag permits a global enable/disable of all enabled interrupt requests. all the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. that is, interrupts can be generated or pending interrupt requests can be cancelled by software. table 15 interrupt source request flag bit location external request 0 internal timer/counter 0 external request 1 internal timer/counter 1 serial interface teletext sync signals analog digital converter ie0 tf0 ie1 tf1 ri/ti dvirst dhirst evenst lin24st avirst ahirst iadc tcon.1 tcon.5 tcon.3 tcon.7 scon.0/.1 ttxsir.2 ttxsir.0 acqsir.6 acqsir.4 acqsir.2 acqsir.0 adcon.5
sda 525x semiconductor group 65 1998-04-08 figure 22 teletext sync signal interrupt system ttxsir.3 display v ttxsir.2 acqsir.5 dvirst ttxsir.1 acqsir.7 acqsir.3 acqsir.1 dviren dhiren evenen lin24en ues05463 aviren ahiren display v display h start of start of acq v acq h even field acq line 24 (each field) interrupt interrupt dhirst ttxsir.0 h display evenst acqsir.6 acq lin24st acqsir.4 interrupt avirst acqsir.2 v acq interrupt ahirst acqsir.0 h acq interrupt acq line 24 interrupt teletext sync signal interrupt tsi even field _ <
sda 525x semiconductor group 66 1998-04-08 figure 23 interrupt system ? seven interrupt sources ? each interrupt can be individually enabled/disabled ? enabled interrupts can be globally enabled/disabled ? each interrupt can be assigned to either of four priority levels ? each interrupt vectors to a separate location in program memory ? interrupt nesting to four levels ? external interrupt requests can be programmed to be level- or transition-activated ie.0 internal 0 external interrupt rqst tcon.7 tcon.3 tcon.5 0 tcon.1 source enable global enable interrupt enable register: input level and interrupt request flag registers: interrupt priority registers: 0 external interrupt ie.3 int ie timer tf 0 timer 1 internal 1 tf 1 ie ie.1 ie.2 ie.4 ie.5 0 ex et 0 ex 1 1 et ea ie.7 ip1.0 ip1.3 ip1.1 ip1.2 ip1.4 ip1.5 ues05465 int 1 0 rqst 1 internal serial port scon ri/ti 1/0 es internal iin eic ip0.0 ip0.1 ip0.2 ip0.3 ip0.4 ip0.5 highest priority level lowest priority level priority sequence ip0.6 ead internal iadc converter digital analog ip1.6 ea ie.6 adcon.5 iccon.4 i 2 c
sda 525x semiconductor group 67 1998-04-08 teletext sync interrupt request register ttxsir teletext sync interrupt request register ttxsir sfr-address c8 h default after reset: 00 h (msb) (lsb) C vsy hsy pclk dviren dvirst dhiren dhirst vsy, hsy, pclk these bits are no interrupt bits. they are described in chapter display special function registers on page 24 . dviren enables or disables the display vertical sync interrupt request. if dviren = 1, this interrupt will be enabled. dvirst display vertical sync interrupt request flag. set by the rising edge of the display vertical sync pulse. must be cleared by software. dhiren enables or disables the display horizontal sync interrupt request. if dhiren = 1, this interrupt will be enabled. dhirst display horizontal sync interrupt request flag. set by the rising edge of the display horizontal sync pulse. must be cleared by software.
sda 525x semiconductor group 68 1998-04-08 acquisition sync interrupt request register acqsir acquisition sync interrupt request register acqsir sfr-address c0 h default after reset: 00 h (msb) (lsb) evenen evenst lin24en lin24st aviren avirst ahiren ahirst evenen enables or disables the even field interrupt request. if evenen = 1, this interrupt will be enabled. evenst even field interrupt request flag. set at the start of even field (field 1). must be cleared by software. lin24en enables or disables the acquisition line 24 interrupt request. if lin24en = 1, this interrupt will be enabled. lin24st acquisition line 24 interrupt request flag. set at the start of acquisition line 24 in each field. must be cleared by software. aviren enables or disables the acquisition vertical sync interrupt request. if aviren = 1, this interrupt will be enabled. avirst acquisition vertical sync interrupt request flag. set by the rising edge of the acquisition vertical sync pulse. must be cleared by software. ahiren enables or disables the acquisition horizontal sync interrupt request. if ahiren = 1, this interrupt will be enabled. ahirst acquisition horizontal sync interrupt request flag. set by the rising edge of the acquisition horizontal sync pulse. must be cleared by software.
sda 525x semiconductor group 69 1998-04-08 interrupt enable register ie interrupt enable register ie sfr-address a8 h default after reset: 00 h (msb) (lsb) ea eadc etsi es et1 ex1 et0 ex0 ea enables or disables all interrupts. if ea = 0, no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. eadc enables or disables the analog digital converter interrupt. if eadc = 1, this interrupt will be enabled. etsi enables or disables the teletext sync interrupts. if etsi = 1, this interrupt will be enabled. es enables or disables the serial interface interrupt. if es = 1, this interrupt will be enabled. et1 enables or disables the timer 1 overflow interrupt. if et1 = 1, the timer 1 interrupt will be enabled. ex1 enables or disables external interrupt 1. if ex1 = 1, external interrupt 1 will be enabled. et0 enables or disables the timer 0 overflow interrupt. if et0 = 1, the timer 0 interrupt will be enabled. ex0 enables or disables external interrupt 0. if ex0 = 1, external interrupt 0 will be enabled.
sda 525x semiconductor group 70 1998-04-08 interrupt priority register ip0 and ip1 corresponding bit-locations in both registers are used to set the interrupt priority level of an interrupt. setting/clearing a bit in the ip-registers establishes its associated interrupt request priority level. if a low-priority level interrupt is being serviced, a higher-priority level interrupt will interrupt it. however, an interrupt source cannot interrupt a service program of the same or higher priority level. interrupt priority register ip0 sfr-address a9 h default after reset: 00 h (msb) (lsb) C ip0.6 ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 interrupt priority register ip1 sfr-address aa h default after reset: 00 h (msb) (lsb) C ip1.6 ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 table 16 ip1.x ip0.x function 0 0 set priority level 0 (lowest) 0 1 set priority level 1 1 0 set priority level 2 1 1 set priority level 3 (highest) table 17 bit corresponding interrupt ip1.0 / ip0.0 ie0 ip1.1 / ip0.1 tf0 ip1.2 / ip0.2 ie1 ip1.3 / ip0.3 tf1 ip1.4 / ip0.4 ri/ti ip1.5 / ip0.5 dvirst/ dhirst/ evenst/ lin24st/avirst/ahirst ip1.6 / ip0.6 iadc
sda 525x semiconductor group 71 1998-04-08 if two requests of different priority levels are received simultaneously, the request of higher priority level will be serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence, see in table 18 . note that the priority within level structure is only used to resolve simultaneous requests of the same priority level. 6.3.4.1 interrupt nesting the process whereby a higher-level interrupt request interrupts a lower-level interrupt service program is called nesting. in this case the address of the next instruction in the lower-priority service program is pushed onto the stack, the stack pointer is incremented by two and processor control is transferred to the program memory location of the first instruction of the higher-level service program. the last instruction of the higher-priority interrupt service program must be a reti-instruction. this instruction clears the higher priority-level-active flip-flop. reti also returns processor control to the next instruction of the lower-level interrupt service program. since the lower priority-level-active flip- flop has remained set, higher priority interrupts are re-enabled while further lower-priority interrupts remain disabled. table 18 source priority within level 1. ie0 2. tf0 3. ie1 4. tf1 5. ri/ti 6. dvirst dhirst evenst lin24st avirst ahirst 7. iadc (highest) (lowest)
sda 525x semiconductor group 72 1998-04-08 6.3.4.2 external interrupts the external interrupt request inputs (int0 and int1 ) can be programmed for either transition- activated or level-activated operation. control of the external interrupts is provided by the four low- order bits of tcon as shown in the follow section. when it0 and it1 are set to one, interrupt requests on int0 and int1 are transition- activated (high-to-low), else they are low-level activated. ie0 and ie1 are the interrupt request flags. these flags are set when their corresponding interrupt request inputs at int0 and int1 , respectively, are low when sampled by the processor and the transition- activated scheme is selected by it0 and it1. function of lower nibble bits in tcon timer and interrupt control register tcon sfr-address 88 h default after reset: 00 h (msb) (lsb) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tcon.4 C tcon.7 see chapter general purpose timers/counters on page 80 . ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. it1 = 1 selects transition-activated external interrupts. ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. it0 = 1 selects transition-activated external interrupts.
sda 525x semiconductor group 73 1998-04-08 C transition-activated interrupts (it0 = 1, it1 = 1) the ie0, ie1 flags are set by a transition at int0 , int1 , respectively; they are cleared during entering the corresponding interrupt service routine. for transition-activated operation, the input must remain active for more than six oscillator periods, but needs not to be synchronous with the oscillator. the opposite transition of a transition-activated input may occur at any time after the six oscillator period latching time, but the input must remain inactive for six oscillator periods before reactivation. C level-activated interrupts (it0 = 0, it1 = 0) the ie0, ie1 flags are set whenever int0, int1 are respectively sampled at low level. sampling int0 , int1 at high level clears ie0, ie1, respectively. for level-activated operation, if the input is active during the sampling that occurs seven oscillator periods before the end of the instruction in progress, an interrupt subroutine call is made. the level-activated input needs to be low only during the sampling that occurs seven oscillator periods before the end of the instruction in progress and may remain low during the entire execution of the service program. however, the input must be deactivated before the service routine is completed to avoid invoking a second interrupt, or else another interrupt will be generated. extension of standard 8051 interrupt logic for more flexibility, the sda 525x family provides a new feature in detection ex0 and ex1 in edge-triggered mode. now there is the possibility to trigger an interrupt on the falling and / or rising edge at the dedicated port3-pin. therefore, an additional register ircon has been defined, which is described on the top. interrupt control register ircon sfr-address ab h default after reset: xxxx0101 b (msb) (lsb) CCCC ex1r ex1f ex0r ex0f ex1r if set, ex1-interrupt detection on rising edge at pin p3.3 ex1f if set, ex1-interrupt detection on falling edge at pin p3.3 ex0r if set, ex0-interrupt detection on rising edge at pin p3.2 ex0f if set, ex0-interrupt detection on falling edge at pin p3.2
sda 525x semiconductor group 74 1998-04-08 6.3.4.3 interrupt task function the processor records the active priority level(s) by setting internal flip-flop(s). each interrupt level has its own flip-flop. the flip-flop corresponding to the interrupt level being serviced is reset when the processor executes a reti-instruction. the sequence of events for an interrupt is: C a source provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred. C the interrupt request is conditioned by bits in the interrupt enable and interrupt priority registers. C the processor acknowledges the interrupt by setting one of the four internal priority- level active flip-flops and performing a hardware subroutine call. this call pushes the pc (but not the psw) onto the stack and, for some sources, clears the interrupt request flag. C the service program is executed. C control is returned to the main program when the reti-instruction is executed. the reti- instruction also clears one of the internal priority-level active flip-flops. the interrupt request flags ie0, ie1, tf0 and tf1 are cleared when the processor transfers control to the first instruction of the interrupt service program. the ri/ti, dvirst, dhirst, evenst, lin24st, avirst, ahirst and iadc-interrupt request flags must be cleared as part of the respective interrupt service program. 6.3.4.4 response time the highest-priority interrupt request gets serviced at the end of the instruction in progress unless the request is made in the last seven (cdc=0) oscillator periods of the instruction in progress. under this circumstance, the next instruction will also execute before the interrupt's subroutine call is made. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the call itself takes two cycles. thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. if the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (mul and div) are only 4 cycles long, and if the instruction in progress is reti or an access to ie or ip0 and ip1, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is mul or div). thus, in a single- interrupt system, the response time is always more than 3 cycles and less than 8 cycles (approximately 2.33 m s at 18-mhz operation). note, that a machine cycle can consist of 12 oscillator periods (cdc = 1) or only six oscillator periods (cdc = 0) (see chapter advanced function register on page 115 ). examples of the best and worst case conditions are illustrated in table 19 .
sda 525x semiconductor group 75 1998-04-08 note: values without brackets apply for cdc = 1 and values in brackets for cdc = 0 (see chapter advanced function register on page 115 ). if an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. 6.3.5 processor reset and initialization processor initialization is accomplished with activation of the rst pin, which is the input to a schmitt trigger. to reset the processor, this pin should be held low for at least four machine cycles, while the oscillator is running stable. upon powering up, rst should be held low for at least 10 ms after the power supply stabilizes to allow the oscillator to stabilize. crystal operation below 6 mhz will increase the time necessary to hold rst low. two machine cycles after receiving of rst , the processor ceases from instruction execution and remains dormant for the duration of the pulse. the high-going transition then initiates a sequence which requires approximately one machine cycle to execute before normal operation commences with the instruction at absolute location 0000 h . program memory locations 0000 h through 0002 h are reserved for the initialization routine of the microcomputer. this sequence ends with registers initialized as shown in chapter memory organization on page 49 . after the processor is reset, all ports are written with one (1). outputs are undefined until the reset period is complete. an automatic reset can be obtained when v dd is turned on by connecting the rst -pin to v ss through a 10 m f capacitor, providing the v dd rise time does not exceed a millisecond and the oscillator start-up time does not exceed 10 milliseconds. when power comes on, the current drawn by rst -pin starts to charge the capacitor. the voltage v rst at rst -pin is the capacitor voltage, and increases to v dd as the capacitor charges. the larger the table 19 instruction time (oscillator periods) best case worst case external interrupt generated immediately before (best) / after (worst) the pin is sampled (time until end of bus cycle). current or next instruction finishes in 12-[6-] oscillator periods next instruction is mul or div internal latency for hardware subroutine call 2 + e[ 1 + e] 12 [6] dont care 24 [12] 2 C e[ 1 C e] 12 [6] 48 [24] 24 [12] 38 [19] 86 [43]
sda 525x semiconductor group 76 1998-04-08 capacitor, the more slowly v rst decreases. v rst must remain below the lower threshold of the schmitt trigger long enough to effect a complete reset. the time required is the oscillator start-up time plus 4 machine cycles. attention: while reset is active and at least four machine cycles after rising edge of rst , ale, p4.0 and p3.6 should not be pulled down externally. otherwise a special production test mode is entered. figure 24 power-on reset circuit power-down operations the controller provides two modes in which power consumption can be significantly reduced. C idle mode. the cpu is gated off from the oscillator. all peripherals are still provided with the clock and are able to work. C power-down mode. operation of the controller is turned off. this mode is used to save the contents of internal ram with a very low standby current. both modes are entered by software. special function register pcon is used to enter one of these modes. ues04722 v rst 10 m f ss dd v v dd ss v rst v
sda 525x semiconductor group 77 1998-04-08 power control register pcon entering the idle mode is done by two consecutive instructions immediately following each other. the first instruction has to set bit idle (pcon.0) and must not set bit idls (pcon.5). the following instruction has to set bit idls (pcon.5) and must not set bit idle (pcon.0). bits idle and idls will automatically be cleared after having been set. this double-instruction sequence is implemented to minimize the chance of unintentionally entering the idle mode. the following instruction sequence may serve as an example: orl pcon,#00000001 b set bit idle, bit idls must not be set. orl pcon,#00100000 b set bit idls, bit idle must not be set. the instruction that sets bit idls is the last instruction executed before going into idle mode. the idle mode can be terminated by activation of any enabled interrupt (or a hardware reset). the cpu-operation is resumed, the interrupt will be serviced and the next instruction to be executed after reti-instruction will be the one following the instruction that set the bit idls. the port state and the contents of sfrs are held during idle mode. entering the power-down mode is done by two consecutive instructions immediately following each other. the first instruction has to set bit pde (pcon.1) and must not set bit pds (pcon.6). the following instruction has to set bit pds (pcon.6) and must not set bit pde (pcon.1). bits pde and pds will automatically be cleared after having been set. this double-instruction sequence is implemented to minimize the chance of power control register pcon sfr-address 87 h default after reset: 000xxx00 (msb) (lsb) smod pds idls C C C pde idle pds power-down start bit. the instruction that sets the pds-flag is the last instruction before entering the power down mode. idls idle start bit. the instruction that sets the pds-flag is the last instruction before entering the idle mode. pde power-down enable bit. when set, starting the power-down mode is enabled. idle idle enable bit. when set, starting the idle mode is enabled. smod baud rate control for serial interface; if set, the baud rate is doubled.
sda 525x semiconductor group 78 1998-04-08 unintentionally entering the power-down mode. the following instruction sequence may serve as an example: orl pcon,#00000010 b set bit pde, bit pds must not be set. orl pcon,#01000000 b set bit pds, bit pde must not be set. the instruction that sets bit pds is the last instruction executed before going into power- down mode. if idle mode and power-down mode are invoked simultaneously, the power-down mode takes precedence. the only exit from power-down mode is a hardware reset. the reset will redefine all sfrs, but will not change the contents of internal ram. 6.3.6 ports and i/o-pins there are 26 i/o-pins configured as three 8-bit ports, one 4-bit-port (p2.0 C 2.3) and one 2-bit port (p4.0 C 4.1, p4.1 for rom-less version only). each pin can be individually and independently programmed as input or output and each can be configured dynamically. an instruction that uses a port's bit/byte as a source operand reads a value that is the logical and of the last value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes that none of the processor's electrical specifications are being violated). an instruction that reads a bit/byte, operates on the content, and writes the result back to the bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. pins comprising a single port can be made a mixed collection of inputs and outputs by writing a one to each pin that is to be an input. each time an instruction uses a port as the destination, the operation must write ones to those bits that correspond to the input pins. an input to a port pin needs not to be synchronized to the oscillator. all the port latches have one s written to them by the reset function. if a zero is subsequently written to a port latch, it can be reconfigured as an input by writing a one to it. the instructions that perform a read of, operation on, and write to a port's bit/byte are inc, dec, cpl, jbc, setb, clr, mov p.x, cjne, djnz, anl, orl, and xrl. the source read by these operations is the last value that was written to the port, without regard to the levels being applied at the pins. this insures that bits written to a one (for use as inputs) are not inadvertently cleared. port 0 has an open-drain output. writing a one to the bit latch leaves the output transistor off, so the pin floats. in that condition it can be used as a high-impedance input. port 0 is considered true bidirectional, because when configured as an input it floats. ports 1, 3 and 4 have quasi-bidirectional output drivers which comprise an internal pullup resistor of 10 k w to 40 k w . when configured as inputs they pull high and will
sda 525x semiconductor group 79 1998-04-08 source current when externally pulled low (for details see chapter dc- characteristics on page 129 ). in ports p1, p3 and p4 the output drivers provide source current for one oscillator period if, and only if, software updates the bit in the output latch from a zero to an one. sourcing current only on zero to one transition prevents a pin, programmed as an input, from sourcing current into the external device that is driving the input pin. secondary functions can be selected individually and independently for the pins of port 1 and 3. further information on port 1's secondary functions is given in chapter pulse width modulation unit (pwm) on page 106 . p3 generates the secondary control signals automatically as long as the pin corresponding to the appropriate signal is programmed as an input, i. e. if the corresponding bit latch in the p3 special function register contains a one. the following alternate functions can be selected when using the corresponding p3 pins: p3.0 odd/even (odd/even-indicator output) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer/counter 0 external input) p3.5 t1 (timer/counter 1 external input) p3.6 rxd (serial port receive line) p3.7 txd (serial port transmit line) read modify-write feature read-modify-write commands are instructions that read a value, possibly change it, and then rewrite it to the latch. when the destination operand is a port or a port bit, these instructions read the latch rather than the pin. the read-modify-write instructions are listed in table 20 . the read-modify-write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin. for example, a port bit might be used to drive the base of a transistor. when a one is written to the bit, the transistor is turned on. if the cpu then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. reading the latch rather than the pin will return the correct value of one.
sda 525x semiconductor group 80 1998-04-08 6.3.7 general purpose timers/counters two independent general purpose 16-bit timers/ counters are integrated for use in measuring time intervals, measuring pulse widths, counting events, and causing periodic (repetitive) interrupts. either can be configured to operate as timer or event counter. in the timer function, the registers tlx and/or thx (x = 0, 1) are incremented once every machine cycle. thus, one can think of it as counting machine cycles. a machine cycle consists of 6 or 12 oscillator periods. this depends on the setting of bit cdc in the advanced function register afr of the special function registers (see chapter advanced function register on page 115 ). for cdc = 1 a machine cycle consists of 12 oscillator periods and for cdc = 0 of 6 oscillator periods. in the counter function, the registers tlx and/or thx (x = 0, 1) are incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled during every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during the cycle following the one in which the transition was detected. since it takes 2 machine cycles (24 oscillator periods for cdc = 1 or 12 oscillator periods for cdc = 0) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency for cdc = 1 or 1/12 of the oscillator frequency for cdc = 0. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. table 20 read-modify-write instructions mnemonic description example anl orl xrl jbc cpl inc dec djnz mov px.y, c (1) clr px.y (1) set px.y (1) logical and logical or logical ex C or jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit y of port x clear bit y of port x set bit y of port x anl p1, a orl p2, a xrl p3, a jbc p1.1, label cpl p3.0 inc p1 dec p1 djnz p3, label mov p1.7, c clr p2.6 set p3.5 (1) the instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch
sda 525x semiconductor group 81 1998-04-08 timer/counter 0: mode selection timer/counter 0 can be configured in one of four operating modes, which are selected by bit-pairs (m1, m0) in tmod-register (see page 83 ). C mode 0 putting timer/counter 0 into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 25 shows the mode 0 operation as it applies to timer 0. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1 s to all 0 s, it sets the timer interrupt flag tf0. the counted input is enabled to the timer when tr0 = 1 and either gate = 0 or int0 = 1. (setting gate = 1 allows the timer to be controlled by external input int0 , to facilitate pulse width measurements.) tr0 is a control bit in the special function register tcon (see page 84 ). gate is contained in register tmod (see page 83 ). the 13-bit register consists of all 8 bits of th0 and the lower 5 bits of tl0. the upper 3 bits of tl0 are indeterminate and should be ignored. setting the run flag (tr0) does not clear the registers. C mode 1 mode 1 is the same as mode 0, except that the timer/counter 0 register is being run with all 16 bits. C mode 2 mode 2 configures the timer/counter 0 register as an 8-bit counter (tl0) with automatic reload, as shown on see page 83 . overflow from tl0 not only sets tf0, but also reloads tl0 with the contents of th0, which is preset by software. the reload leaves th0 unchanged. C mode 3 timer/counter 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 27 . tl0 uses the timer 0 control bits: c/t, gate, tr0, int0 and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. with timer 0 in mode 3, the processor can operate as if it has three timers/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used in any application not requiring an interrupt.
sda 525x semiconductor group 82 1998-04-08 timer/counter 1: mode selection timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (m1, m0) in tmod-register. the serial port receives a pulse each time that timer/counter 1 overflows. this pulse rate is divided to generate the transmission rate of the serial port. modes 0 and 1 are the same as for counter 0. C mode 2 the reload mode is reserved to determine the frequency of the serial clock signal (not implemented). C mode 3 when counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables the increment counter. this mode is provided as an alternative to using the tr1 bit (in tcon-register) to start and stop timer/counter 1. configuring the timer/counter input the use of the timer/counter is determined by two 8-bit registers, tmod (timer mode) and tcon (timer control), as shown on page 83 and 84 . the input to the counter circuitry is from an external reference (for use as a counter), or from the on-chip oscillator (for use as a timer), depending on whether tmod's c/t-bit is set or cleared, respectively. when used as a time base, the on-chip oscillator frequency is divided by twelve or six ( see figure 25, 26 and 26 ) before being used as the counter input. when tmod's gate bit is set (1), the external reference input (t1, t0) or the oscillator input is gated to the counter conditional upon a second external input (int0) , (int1 ) being high. when the gate bit is zero (0), the external reference, or oscillator input, is unconditionally enabled. in either case, the normal interrupt function of int0 and int1 is not affected by the counter's operation. if enabled, an interrupt will occur when the input at int0 or int1 is low. the counters are enabled for incrementing when tcon's tr1 and tr0 bits are set. when the counters overflow, the tf1 and tf0 bits in tcon get set, and interrupt requests are generated. the counter circuitry counts up to all 1's and then overflows to either 0's or the reload value. upon overflow, tf1 or tf0 is set. when an instruction changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. the t1 and t0 inputs are sampled near the falling-edge of ale in the tenth, twenty- second, thirty-fourth and forty-sixth oscillator periods of the instruction-in-progress (cdc=1). thus, an external reference's high and low times must each have a minimum duration of twelve oscillator periods for cdc = 1 or six oscillator periods for cdc = 0. there is a twelve (cdc = 1) or six (cdc = 0) oscillator period delay from the time when a toggled input (transition from high to low) is sampled to the time when the counter is incremented.
sda 525x semiconductor group 83 1998-04-08 timer/counter mode register timer 0/1 mode register tmod sfr-address 89 h default after reset: 00 h (msb) (lsb) gate c/t m1 m0 gate c/t m1 m0 gate gating control when set. timer/counter x is enabled only while intx pin is high and trx control bit is set. when cleared, timer x is enabled, whenever trx control bit is set. c/t timer or counter selector. cleared for timer operation (input from internal system clock). set for counter operation (input from tx input pin). table 21 m1 m0 operating mode 0 0 1 1 0 1 0 1 sab 8048 timer: tlx serves as five-bit prescaler. 16-bit timer/counter: thx and tlx are cascaded, there is no prescaler. 8-bit auto-reload timer/counter: thx holds a value which is to be reloaded into tlx each time it overflows. (timer 0) tl0 is an eight-bit timer/counter controlled by the standard timer 0 control bits; th0 is an eight-bit timer only controlled by timer 1 control bits. (timer 1) timer/counter 1 is stopped. timer 1 timer 0
sda 525x semiconductor group 84 1998-04-08 timer/counter control register timer 0/1 mode register tcon sfr-address 88 h default after reset: 00 h (msb) (lsb) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it1 interrupt 1 type control bit. set/cleared by software to specify edge/low level triggered external interrupts. ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it0 interrupt 0 type control bit. set/cleared by software to specify edge/low level triggered external interrupts.
sda 525x semiconductor group 85 1998-04-08 figure 25 timer/counter 0 mode 0: 13-bit counter figure 26 timer/counter 0 mode 2: 8-bit auto-reload c/t = 1 control interrupt gate ues04602 int0 pin 1 1 & c/t = 0 tl0 th0 tf0 tr0 (5 bits) (8 bits) machine cycles cdc = 1 cdc = 0 6 12 osc t0 pin _ < . . . . c/t = 1 control osc gate int0 pin t0 pin 12 1 1 & c/t = 0 tl0 tf0 tr0 reload ues04603 th0 (8 bits) (8 bits) 6 cdc = 0 cdc = 1 machine cycles interrupt _ < . . . .
sda 525x semiconductor group 86 1998-04-08 figure 27 timer/counter 0 mode 3: two 8-bit counters control 0 1 & tf fm fm tf 1 control 1 tr machine cycles osc fm ues04604 interrupt interrupt cdc = 1 cdc = 0 c/t = 0 c/t = 1 tr0 t0 pin gate int0 pin < _ 1 (8 bits) th0 (8 bits) tl0 6 . . 12 . .
sda 525x semiconductor group 87 1998-04-08 6.3.8 watchdog timer to protect the systems against software upset, the user's program has to clear this watchdog within a previously programmed time period. if the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. the software can be designed so that the watchdog times out if the program does not work properly. the watchdog timer is a 15-bit timer, which is incremented by a count rate of either f cycle /2 or f cycle /128. the latter is enabled by setting bit wdtrel.7. note, that f cycle can be f quarz /12 for cdc = 1 or f quarz /6 for cdc = 0 (see chapter advanced function register on page 115 ). immediately after start, the watchdog timer is initialized to the reload value programmed to wdtrel.0 C wdtrel.6. after an external reset register wdtrel is cleared to 00 h . the lower seven bits of wdtrel can be loaded by software at any time. the watchdog timer is started by software by setting bit swdt in special function register wdcon (bit 6). if the counter is stopped, and wdtrel is loaded with a new value, wdth (high-byte of the watchdog timer) is updated immediately. wdtl (low-byte of the watchdog timer) is always zero, if the counter is stopped. once started the watchdog timer cannot be stopped by software but can only be refreshed to the reload value by first setting bit wdt (afr.6) and by the next instruction setting swdt (wdcon.6). bit wdt will automatically be cleared during the third machine cycle after having been set. this double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog. if the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7fff h . the duration of the reset signal then depends on the prescaler selection. this internal reset differs from an external reset only in so far as the watchdog timer is not disabled and bit wdts (wdcon.7) is set. bit wdts allows the software to examine from which source the reset was activated. the watchdog timer status flag can also be cleared by software. with wdtrel = 80 h and an oscillator frequency of 18 mhz the maximum time period is about 0.7 s for cdc = 0 and about 1.4 s for cdc = 1.
sda 525x semiconductor group 88 1998-04-08 watchdog timer control bits watchdog timer reload register wdtrel sfr-address 86 h default after reset: 00 h (msb) (lsb) wdtrel.7 wdtrel.6 wdtrel.5 wdtrel.4 wdtrel.3 wdtrel.2 wdtrel.1 wdtrel.0 wdtrel.7 prescaler bit. when set, the watchdog is clocked through an additional divide-by-64 prescaler. wdtrel.0 - wdtrel.6 seven bit reload value for the high-byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt. watchdog timer control register wdcon sfr-address a7 h default after reset: 00 h (msb) (lsb) wdts swdt CCCCCC wdts watchdog timer reset flag. if bit wdts is 1 after reset, the reset has been initiated by the watchdog timer. after external reset, wdts is reset to 0. swdt watchdog timer start flag. set to activate the watchdog timer. when directly set after setting wdt, a watchdog timer refresh is performed. wdcon.0 - wdcon.5 reserved.
sda 525x semiconductor group 89 1998-04-08 advanced function register afr advanced function register afr sfr-address a6 h default after reset: 00xxxxxx b (msb) (lsb) cdcwdt000000 cdc see chapter advanced function register on page 115 . wdt watchdog timer refresh flag. set to initiate a refresh of the watchdog timer. must be set directly before swdt (wdcon.6) is set to the watchdog timer. afr.0 - afr.5 reserved, always to be written with 0.
sda 525x semiconductor group 90 1998-04-08 6.3.9 capture compare timer for easier infrared signal decoding, an additional capture compare timer is implemented. a functional overview is given in following feature list: C 16-bit-counter with 2 or 3 prescaler bits selectable via sfr C counting rate: internal clock (18 mhz) C counter reloadable, prescaler bits reload with 0 C capture function C timer polling mode C p3.3 or p3.2 selectable as capture input C capture on rising and/or falling edge C overflow-bit infrared timer control register irtcon note: if counter is halted, a counter-reload with the contents of the reload registers is forced by hardware to give the counter a starting value. infrared timer control register irtcon sfr-address e5 h default after reset: 00 h (msb) (lsb) ov pr plg rel run rise fall sel ov will be set by hardware, if counter overflow has occurred; must be cleared by software pr if cleared, 2-bit prescaler; if set, 3-bit prescaler plg if set, timer polling mode selected, capture function is automatically disabled, reading capture registers will now show current timer value rel if set, counter will be reloaded simultaneously with capture event run run/stop the counter rise capture (and if rel=1, reload) on rising edge fall capture (and if rel=1, reload) on falling edge sel if set, p3.3 is selected for capture input, otherwise p3.2
sda 525x semiconductor group 91 1998-04-08 the registers relh and rell (sfr-address e2 h and e1 h ) are the reload registers, caph and capl (sfr-addresses e4 h and e3 h ) are the corresponding capture registers. the reset value of these registers is undefined. 6.3.10 serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the frequencies and baud rates described in this chapter depend on the internal system clock, used by the serial interface. the internal system clock frequency of the serial interface is defined by the oscillator frequency f osc and the setting of bit cdc in the advanced function register afr of the special function registers (see chapter advanced function register on page 115 ). the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd (p3.6). txd (p3.7) outputs the shift clock. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on reception, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmission, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on reception, the 9th data bit goes into rb8 in the special function register scon, while the stop bit is ignored. the baud rate is programmable via sfr-bit smod. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit and a stop bit (1 ). in fact, mode 3 is the same as mode 2 in all respects except the baud rate. the baud rate in mode 3 is variable.
sda 525x semiconductor group 92 1998-04-08 serial port control register scon serial port control register scon sfr-address 98 h default after reset: 00 h (msb) (lsb) sm0 sm1 sm2 ren tb8 rb8 ti ri sm0 sm1 serial port mode selection, see table 22 . sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1 then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. cleared by software to disable reception. tb8 is the 9th data bit that will be transmitted in modes 2 and 3. set or cleared by software as desired. rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti is the transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. ri is the receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. must be cleared by software.
sda 525x semiconductor group 93 1998-04-08 in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition rl = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. the control, mode, and status bits of the serial port in special function register scon are illustrated on page 92 . 6.3.10.1 multiprocessor communication modes 2 and 3 of the serial interface of the controller have a special provision for multiprocessor communication. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor communications is as follows. when the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. table 22 serial port mode selection sm0 sm1 mode description baud rate (cdc = 0) 0 0 0 shift reg. f osc /6 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32, f osc /16 1 1 3 9-bit uart variable
sda 525x semiconductor group 94 1998-04-08 6.3.10.2 baud rates the baud rate in mode 0 is fixed: the baud rate in mode 2 depends on the value of bit smod in special function register pcon (bit 7). if smod = 0 (which is the value on reset), the baud rate is 1/32 of the oscillator frequency. if smod = 1, the baud rate is 1/16 of the oscillator frequency. the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate or can be generated by the internal baud rate generator. when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operation, and in any of the 3 running modes. in the most typical applications, it is configured for timer operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case, the baud rate is given by the formula: one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. mode 0 baud rate f osc 6 -------------- = mode 2 baud rate 2 smod 32 ------------------ f osc = mode 1, 3 baud rate 2 smod 16 ------------------ time 1 overflow = mode 1, 3 baud rate 2 smod 16 ------------------ f osc 12 256 th1 e () --------------------------------------------- =
sda 525x semiconductor group 95 1998-04-08 6.3.10.3 more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (lsb first). figure 28 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the write-to sbuf signal also loads a 1 into the 9th bit position of the transmit shift register and tells the tx-control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between write-to-sbuf and activation of send. send enables the output of the shift register to the alternate output function line of p3.6, and also enables shift clock to the alternate output function, line of p3.7. at the end of every machine cycle in which send is active, the contents of the transmit shift register is shifted one position to the right. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just left of the msb, and all positions to the left of that contain zeros. this condition flags the tx-control block to do one last shift and then deactivate send and set tl. both of these actions occur in the 10th machine cycle after write-to-sbuf. reception is initiated by the condition ren = 1 and rl = 0. at the end of the next machine cycle, the rx-control unit writes the bits 1111 1110 to the receive shift register, and the next clock phase activates receive. receive enables shift clock to the alternate output function line of p3.7. at the end of every machine cycle in which receive is active, the contents of the receive shift register are shifted one position to the left. the value that comes in from the right is the value that was sampled at the p3.6 pin in the same machine cycle. as data bits come in from the right, 1 s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the rx-control block to do one last shift and load sbuf. in the 10th machine cycle after the write to scon that cleared rl, receive is cleared and rl is set. 6.3.10.4 more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first) and a stop bit (1). on reception, the stop bit goes into rb8 in scon. the baud rate is determined by the timer 1 overflow rate. figure 30 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit and receive. transmission is initiated by any instruction that uses sbuf as a destination register. the write-to sbuf signal also loads a 1 into the 9th bit position of the transmit shift register and flags the tx- control block that a transmission is requested. transmission actually
sda 525x semiconductor group 96 1998-04-08 commences at the beginning of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the write-to-sbuf signal). the transmission begins with activation of send , which puts the start bit to txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just left of the msb, and all positions to the left of that contain zeros. this condition flags the tx-control unit to do one last shift and then deactivate send and set tl. this occurs at the 10th divide-by-16 rollover after write-to-sbuf. reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1 ff h is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1 s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the rx-control block to do one last shift, load sbuf and rb8, and set rl. the signal to load sbuf and rb8, and to set rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. rl = 0, and 2. either sm2 = 0 or the received stop bit = 1 if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf and rl is activated. at this time, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition in rxd. 6.3.10.5 more about modes 2 and 3 11 bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit, (1). on transmission, the 9th data bit (tb8) can be assigned the value of 0 or 1. on reception, the 9th data bit goes into rb8 in scon.
sda 525x semiconductor group 97 1998-04-08 figures 32 and 34 show a functional diagram of the serial port in modes 2 and 3 and associated timings. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the write-to- sbuf signal also loads tb8 into the 9th bit position of the transmit shift register and flags the tx- control unit that a transmission is requested. transmission commences at the beginning of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the write-to-sbuf signal). the transmission begins with activation of send , which puts the start bit to txd. one bit time later, data is activated which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just left of the tb8, and all positions to the left of that contain zeros. this condition flags the tx-control unit to do one last shift and then deactivate send and set tl. this occurs at the 11th divide-by-16 rollover after write-to-sbuf. reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ff h is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1 s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx-control block to do one last shift, load sbuf and rb8, and set rl. the signal to load sbuf and rb8, and to set rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. rl = 0, and 2. either sm2 = 0 or the received 9th data bit = 1 if either of these two conditions is not met, the received frame is irretrievably lost, and rl is not set. if both conditions are met, the received 9th data bit goes into rb8, the first 8 data bits go into sbuf. one bit time later, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition at the rxd input. note that the value of the received stop bit is irrelevant to sbuf, rb8 or rl.
sda 525x semiconductor group 98 1998-04-08 figure 28 serial port mode 0, functional diagram ues04726 internal bus 1 sbuf zero detector d s cl q shift send 1 tx control start tx clock ti rx control start ri receive shift serial port interrupt input shift register sbuf internal bus write to sbuf shift load sbuf read sbuf rxd p3.6 alt. output function function output p3.7 alt. txd 1 shift clock & ren ri clock rx clock function input p3.6 alt. rxd 0 1 111111 & & _ < _ <
sda 525x semiconductor group 99 1998-04-08 figure 29 serial port mode 0, timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 write to sbuf send shift rxd (data out) txd (shift clock) ti write to scon (clear ri) receive shift rxd (data in) ri txd (shift clock) receive transmit ued04727
sda 525x semiconductor group 100 1998-04-08 figure 30 serial port mode 1, functional diagram ues04728 internal bus 1 sbuf zero detector d s cl q data send 1-to-0 transition detector tx control shift start tx clock rx control start load shift sbuf sample bit detector (9 bits) input shift register 1ff sbuf internal bus write to sbuf txd rxd shift load sbuf read sbuf & h 16 rx clock interrupt port serial 1 ti ri 2 smod=1 smod=0 (pcon.7) timer1 overflow _ < . . . . . . 16 1 < _
sda 525x semiconductor group 101 1998-04-08 figure 31 serial port mode 1, timing write to sbuf tx clock send data shift txd ti rx clock shift ri rxd transmit ued04729 start bit d0 d1 d2 d3 d4 d5 d6 d7 bit stop stop bit d7 d6 d5 d4 d3 d2 d1 d0 bit start 16 reset bit detector sample times receive
sda 525x semiconductor group 102 1998-04-08 figure 32 serial port mode 2, functional diagram ues04730 internal bus tb8 sbuf zero detector d s cl q data send 1-to-0 transition detector tx control shift start tx clock rx control start load shift sbuf sample bit detector (9 bits) input shift register 1ff sbuf internal bus write to sbuf txd rxd shift load sbuf read sbuf & h rx clock interrupt port serial ti ri smod=1 smod=0 (pcon.7) phase 2 clk stop bit gen. . . 2 . . 16 16 . . 1 < _ 1 _ <
sda 525x semiconductor group 103 1998-04-08 figure 33 serial port mode 2, timing write to sbuf tx clock send data shift txd ti rx clock shift ri rxd transmit ued04731 start bit d0 d1 d2 d3 d4 d5 d6 d7 tb8 bit stop stop bit rb8 d7 d6 d5 d4 d3 d2 d1 d0 bit start 16 reset bit detector sample times receive stop bit gen.
sda 525x semiconductor group 104 1998-04-08 figure 34 serial port mode 3, functional diagram ues04732 internal bus tb8 sbuf zero detector d s cl q data send 1-to-0 transition detector tx control shift start tx clock rx control start load shift sbuf sample bit detector (9 bits) input shift register 1ff sbuf internal bus write to sbuf txd rxd shift load sbuf read sbuf & h rx clock interrupt port serial ti ri smod=1 smod=0 (pcon.7) timer1 overflow . . 2 . . 16 16 . . 1 < _ 1 _ <
sda 525x semiconductor group 105 1998-04-08 figure 35 serial port mode 3, timing write to sbuf tx clock send data shift txd ti rx clock shift ri rxd transmit ued04733 start bit d0 d1 d2 d3 d4 d5 d6 d7 tb8 bit stop stop bit rb8 d7 d6 d5 d4 d3 d2 d1 d0 bit start 16 reset bit detector sample times receive
sda 525x semiconductor group 106 1998-04-08 6.3.11 pulse width modulation unit (pwm) the on-chip-pwm unit consists of 6 quasi-8-bit and 2 quasi-14-bit pwm channels. controlled via special function registers, each channel can be enabled individually. the base frequency of an 8-bit channel is derived from the overflow of a 6-bit counter which counts internal clocks. on every counter overflow, the enabled pwm lines will be set to one (exception: compare values are zero) and will be reset when the 6 msbs of the pwcompx-register match the counter value. to get an overall resolution of 8 bit, the high-time is stretched periodically, depending on the 2 lsbs of the pwcompx-register. for example, if pwcompx[1:0] is 10, the high-time will be stretched in every second base cycle. this type of pwm channel is called 6 plus 2. figure 36 simplified example with pwcompx[1:0]= 10 the function of an 14-bit channel is very similar. here, an 8-bit counter gives the base frequency. all 8 bits of the pwcompx registers are compared with the counter value, and the value in pwextx register gives the number of stretchings within 64 successive base cycles. thus, this type of pwm channel is called 8 plus 6. the table 24 shows the influence of the pwextx register bits on cycles to be stretched. table 23 effect of pwcompx-bits for 8-bit pwm pwcompx cycle number stretched bit 1 bit 0 1,3 2 stretched cycle 1 cycle 2 cycle 3 cycle 0
sda 525x semiconductor group 107 1998-04-08 further details of the pwm unit the pwm-output channels are placed as alternate functions to the eight lines of port 1. p1.0 ... p1.5 contain the 6 output channels with 8-bit resolution and p1.6 ... p1.7 the 2 output channels with 14-bit resolution. each pwm-channel can be individually switched between pwm-function and port function. the six 8-bit compare registers pwcomp0 C pwcomp5 are located at sfr-addresses 0f1 h C 0f6 h . the two 14-bit compare registers consist each of an 8-bit register pwcomp6 or pwcomp7 and of a six-bit extension register pwext6 or pwext7, all located at sfr-addresses 0fa h C 0fd h . they contain the modulation ratios of the output signals, which are related to the maximum, defined by the counters resolution. these compare registers are double buffered and a new compare value will only be taken into the main register, after the next timer overflow or if the pwm-timer is stopped. the pwm-timer registers located at sfr-address f7 and f9 h contain the actual value of the pwm-counter low byte and high byte and can only be read by the cpu. every compare register, which is not employed for the pwm-output can be used as an additional register. this is not allowed for register pwme. the internal timer of the pwm unit is running as long as at least one pwm-channel is enabled by the pwm-enable register pwme. table 24 effect of pwextx-bits for 14-bit pwm pwextx cycle number stretched bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1,3,5,7,...,59,61,63 2,6,10,...,54,58,62 4,12,20,...,52,60 8,24,40,56 16,48 32 no effect no effect table 25 base frequencies pwm resolution base frequency 8 bit f osc / 2 cdc x 64 14 bit f osc / 2 cdc x 256
sda 525x semiconductor group 108 1998-04-08 pwm-enable register pwme pwm compare registers pwcomp 0 - 5 pwm-enable register pwme sfr-address f8 h default after reset: 00 h (msb) (lsb) e7 e6 e5 e4 e3 e2 e1 e0 e7 - e0 = 0 the corresponding pwm-channel is disabled. p1.i functions as normal bidirectional i/o-port. = 1 he corresponding pwm-channel is enabled. e0...e5 are channels with 8-bit resolution, while e6 and e7 are channels with 14-bit resolution. pwm compare registers pwcomp 0 - 5 sfr-address f1 h -f6 h default after reset: 00 h (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 - bit 2 this bits define the high time of the output. if all bits are 0, the high time is 0 internal clocks. if all bits are 1, the high time is 63 internal clocks. bit 1 if this bit is set, every second pwm-cycle is stretched by one internal clock, regardless of the settings of bit7...bit2. bit 0 if this bit is set, every fourth pwm-cycle is stretched by one internal clock, regardless of the settings of bit7...bit2.
sda 525x semiconductor group 109 1998-04-08 pwm compare registers pwcomp 6, 7 pwm extension registers pwext 6, 7 note: the described operation is independent of the setting of pwcomp6 or pwcomp7. the stretch operation is interleaved between pwm-cycles. pwm compare registers pwcomp 6, 7 sfr-address fb h ,fd h default after reset: 00 h (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 - bit 0 this bits define the high time of the output. if all bits are 0, the high time is 0 internal clocks. if all bits are 1, the high time is 255 internal clocks. pwm extension registers pwext 6, 7 sfr-address fa h ,fc h default after reset: 00 h (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 if this bit is set, every second pwm-cycle is stretched by one internal clock. bit 6 if this bit is set, every fourth pwm-cycle is stretched by one internal clock. bit 5 if this bit is set, every eighth pwm-cycle is stretched by one internal clock. bit 4 if this bit is set, every 16th pwm-cycle is stretched by one internal clock. bit 3 if this bit is set, every 32th pwm-cycle is stretched by one internal clock. bit 2 if this bit is set, every 64th pwm-cycle is stretched by one internal clock. bit 1, bit 0 this bits have to be set to 0.
sda 525x semiconductor group 110 1998-04-08 pwm low counter registers pwcl pwm high counter registers pwch pwm low counter registers pwcl sfr-address f7 h default after reset: 00 h (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 - bit 0 this bits are the low order 8 bits of the 14 bit pwm-counter. this register can only be read. pwm high counter registers pwch sfr-address f9 h default after reset: 00 h (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7, bit 6 this bits are undefined. bit 5 - bit 0 this bits are the high order 6 bits of the 14 bit pwm-counter. this register can only be read.
sda 525x semiconductor group 111 1998-04-08 figure 37 block diagram of pulse width modulation unit 1.0 8 pwm-channel 0 pwm-channel 2 pwm-channel 3 pwm-channel 4 pwm-channel 5 pwm-channel 6 pwm-channel 7 pwm-channel 1 pwm-timer enable register e7 e6 e1 e0 internal bus ued09860 p p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit 14 bit 14 bit
sda 525x semiconductor group 112 1998-04-08 6.3.12 analog digital converter the controller provides an a/d-converter with the following features: C 4 multiplexed input channels, which can also be used as digital inputs C 8-bit resolution C 8.89 to 28.4 m s conversion time for 18 mhz oscillator frequency C analog reference voltages supplied by pins v dda and v ssa the conversion time depends on the internal master clock, used by the adc. the clock- frequency of the internal adc master clock is defined by the external quartz (oscillator frequency f osc ), the setting of bit cdc in the advanced function register afr of the special function registers (sfr) (see chapter advanced function register on page 115 ), and the setting of bit psc in the adc control register adcon (sfr). both bits are software switches to activate or deactivate clock dividers by 2. the conversion time further depends on the sample time, adjustable by bit stadc (adc-control register adcon). the conversion time can be calculated by: for the conversion, the method of successive approximation via capacitor array is used. there are three user-accessible special function registers: adcon, addat and dapr. special function register adcon is used to set the operation modes, to check the status and to select one of four input channels. adcon contains two mode bits. bit adm is used to choose the single or continuous conversion method. in single conversion mode (adm = 0) only one conversion is performed after starting, while in continuous conversion mode (adm = 1) a new conversion is automatically started on completion of the previous one. the busy flag bsy (adcon.4) is automatically set when a conversion is in progress. after completion of the conversion it is reset by hardware. this flag can be read only, a write has no effect. mx0 and mx1 are used to select one of 4 a/d- channels. with psc a divide by two prescaler for the internal master clock of the adc can be activated. for psc = 0 the internal chip-clock is used as master clock for the adc. for psc = 1 the internal chip-clock is divided by two before being used as master clock for the adc. with bit stadc the sample time of the adc can be varied. bit stadc = 0 selects the normal sample time (sample time of 2 adc master clock cycles), while for stadc = 1 the sample time is slowed down by a factor of 4 (sample time of 8 adc master clock cycles) e.g. for high-impedance input signals. the special function register addat holds the converted digital 8-bit data result. the data remains in addat until it is overwritten by the next converted data. addat can be read or written under software control. a start of conversion is triggered by a write-to dapr instruction. the data written must be 00 h . t conversion 2 2 stadc 4 + () 32 2 cdc 2 psc f osc --------------------------------------------------------------------------------------------- - =
sda 525x semiconductor group 113 1998-04-08 figure 38 internal system clock of the adc adc-start register dapr only the address of dapr is used to decode a start-of-conversion signal. no bits are implemented. a read from dapr might show random values. adc-start register dapr sfr-address da h default after reset: 00 h (msb) (lsb) CCCCCCCC ues09861 cdc = 0 cdc = 1 chip clock 2 osc 6 internal instruction cycles machine cycles, 2 psc = 0 psc = 1 system clock for adc internal
sda 525x semiconductor group 114 1998-04-08 adc-control register adcon this register is bit addressable. adc-control register adcon sfr-address d8 h default after reset: 00 h (msb) (lsb) psc stadc iadc bsy adm 0 mx1 mx0 psc prescaler control: psc = 0 for prescaler not active. internal master clock of adc is equal to the internal chip clock. psc = 1 for prescaler active. internal master clock of adc is at half the internal chip clock. stadc adc sample time adjustment: stadc = 0 for normal sample time. stadc = 1 for fourfold sample time. iadc adc interrupt request flag. set on completion of ad- conversion. must be cleared by software. bsy busy flag; = 1, during conversion. adm adc-conversion mode: adm = 0 for single and adm = 1 for continuous conversion. adcon.2 always to be written with 0. mx1, mx0 adc-channel select. table 26 adc-channel select mx1 mx0 selected channel 000 011 102 113
sda 525x semiconductor group 115 1998-04-08 adc-data register addat 6.3.13 advanced function register the machine cycle time is controlled by bit cdc too. for cdc = 1 a machine cycle consists of 12 oscillator cycles and for cdc = 0 of six oscillator cycles (see figure 14 ). adc-data register addat sfr-address d9 h default after reset: undefined (msb) (lsb) ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ad (7-0) 8-bit analog data value advanced function register afr sfr-address a6 h default after reset: 00xxxxxxb (msb) (lsb) cdcwdt000000 cdc clock divider control bit. if set, the clock divider is on. the internal clock frequency is half the external oscillator frequency. if cleared, the clock divider is off. the internal clock frequency is equal to the external oscillator frequency. this feature can be used to reduce power dissipation by reducing the internal clock frequency by a factor of two. wdt see chapter watchdog timer on page 87 . afr.0 C afr.5 reserved, always to be written with 0.
sda 525x semiconductor group 116 1998-04-08 6.3.14 instruction set the assembly language uses the same instruction set and the same instruction opcodes as the 8051 microcomputer family. 6.3.14.1 notes on data addressing modes rn C working register r0 C r7. direct C 128 internal ram-locations, any i/o-port, control or status register. @ri C indirect internal ram-location addressed by register r0 or r1. #data C 8-bit constant included in instruction. #data 16 C 16-bit constant included as bytes 2 & 3 of instruction. bit C 128 software flags, any i/o-pin, control or status bit in special function registers. operations working on external data memory (movx ) are used to access the extended internal data ram (xram). 6.3.14.2 notes on program addressing modes addr 16 C destination address for lcall & ljmp may be anywhere within the program memory address space. addr 11 C destination address for acall & ajmp will be within the same 2 kbyte of the following instruction. rel C sjmp and all conditional jumps include an 8-bit offset byte. range is + 127/ C 128 bytes relative to first byte of the following instruction.
sda 525x semiconductor group 117 1998-04-08 6.3.14.3 instruction set description table 27 arithmetic operations mnemonic description byte add a, rn add register to accumulator 1 add a, direct add direct byte to accumulator 2 add a, @ri add indirect ram to accumulator 1 add a, #data add immediate data to accumulator 2 addc a, rn add register to accumulator with carry flag 1 addc a, direct add direct byte to a with carry flag 2 addc a, @ri add indirect ram to a with carry flag 1 addc a, #data add immediate data to a with carry flag 2 subb a, rn subtract register from a with borrow 1 subb a, direct subtract direct byte from a with borrow 2 subb a, @ri subtract indirect ram from a with borrow 1 subb a, #data subtract immediate data from a with borrow 2 inc a increment accumulator 1 inc rn increment register 1 inc direct increment direct byte 2 inc @ri increment indirect ram 1 dec a decrement accumulator 1 dec rn decrement register 1 dec direct decrement direct byte 2 dec @ri decrement indirect ram 1 inc dptr increment data pointer 1 mul ab multiply a & b 1 div ab divide a & b 1 da a decimal adjust accumulator 1
sda 525x semiconductor group 118 1998-04-08 table 28 logical operations mnemonic description byte anl a, rn and register to accumulator 1 anl a, direct and direct byte to accumulator 2 anl a, @ri and indirect ram to accumulator 1 anl a, #data and immediate data to accumulator 2 anl direct, a and accumulator to direct byte 2 anl direct, #data and immediate data to direct byte 3 orl a, rn or register to accumulator 1 orl a, direct or direct byte to accumulator 2 orl a, @ri or indirect ram to accumulator 1 orl a, #data or immediate data to accumulator 2 orl direct, a or accumulator to direct byte 2 orl direct, #data or immediate data to direct byte 3 xrl a, rn exclusive-or register to accumulator 1 xrl a, direct exclusive-or direct byte to accumulator 2 xrl a, @ri exclusive-or indirect ram to accumulator 1 xrl a, #data exclusive-or immediate data to accumulator 2 xrl direct, a exclusive-or accumulator to direct byte 2 xrl direct, #data exclusive-or immediate data to direct 3 clr a clear accumulator 1 cpl a complement accumulator 1 rl a rotate accumulator left 1 rlc a rotate a left through the carry flag 1 rr a rotate accumulator right 1 rrc a rotate a right through carry flag 1 swap a swap nibbles within the accumulator 1
sda 525x semiconductor group 119 1998-04-08 1) not applicable for the sda525x table 29 data transfer operations mnemonic description byte mov a, rn move register to accumulator 1 mov a, direct move direct byte to accumulator 2 mov a, @ri move indirect ram to accumulator 1 mov a, #data move immediate data to accumulator 2 mov rn, a move accumulator to register 1 mov rn, direct move direct byte to register 2 mov rn, #data move immediate data to register 2 mov direct, a move accumulator to direct byte 2 mov direct, rn move register to direct byte 2 mov direct, direct move direct byte to direct 3 mov direct, @ri move indirect ram to direct byte 2 mov direct, #data move immediate data to direct byte 3 mov @ri, a move accumulator to indirect ram 1 mov @ri, direct move direct byte to indirect ram 2 mov @ri, #data move immediate data to indirect ram 2 mov dptr, #data 16 load data pointer with a 16-bit constant 3 movc a@a + dptr move code byte relative to dptr to accumulator 1 movc a@a + pc move code byte relative to pc to accumulator 1 movx a, @ri move external ram (8-bit addr) to accumulator 1) 1 movx a, @dptr move external ram (16-bit addr) to accumulator 1 movx @ri, a move a to external ram (8-bit addr) 1) 1 movx @dptr, a move a to external ram (16-bit addr) 1 push direct push direct byte onto stack 2 pop direct pop direct byte from stack 2 xch a, rn exchange register with accumulator 1 xch a, direct exchange direct byte with accumulator 2 xch a, @ri exchange indirect ram with accumulator 1 xchd a, @ri exchange low-order digital indirect ram with a 1) 1
sda 525x semiconductor group 120 1998-04-08 table 30 boolean variable manipulation mnemonic description byte clr c clear carry flag 1 clr bit clear direct bit 2 setb c set carry flag 1 setb bit set direct bit 2 cpl c complement carry flag 1 cpl bit complement direct bit 2 anl c, bit and direct bit to carry flag 2 anl c, /bit and complement of direct bit to carry 2 orl c, bit or direct bit to carry flag 2 orl c, /bit or complement of direct bit to carry 2 mov c, bit move direct bit to carry flag 2 mov bit, c move carry flag to direct bit 2
sda 525x semiconductor group 121 1998-04-08 table 31 program and machine control operations mnemonic description byte acall addr 11 absolute subroutine call 2 lcall addr 16 long subroutine call 3 ret return from subroutine 1 reti return from interrupt 1 ajmp addr 11 absolute jump 2 ljmp addr 16 long jump 3 sjmp rel short jump (relative addr) 2 jmp @a + dptr jump indirect relative to the dptr 1 jz rel jump if accumulator is zero 2 jnz rel jump if accumulator is not zero 2 jc rel jump if carry flag is set 2 jnc rel jump if carry flag is not set 2 jb bit, rel jump if direct bit set 3 jnb bit, rel jump if direct bit not set 3 jbc bit, rel jump if direct bit is set and clear bit 3 cjne a, direct rel compare direct to a and jump if not equal 3 cjne a, #data, rel compare immediate to a and jump if not equal 3 cjne rn, #data, rel compare immediate to register and jump if not equal 3 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 djnz rn, rel decrement register and jump if not zero 2 djnz direct, rel decrement direct and jump if not zero 3 nop no operation 1
sda 525x semiconductor group 122 1998-04-08 6.3.15 instruction opcodes in hexadecimal order table 32 instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 nop ajmp ljmp rr inc inc inc inc inc inc inc inc inc inc inc inc jbc acall lcall rrc dec dec dec dec dec dec dec dec dec dec dec dec jb ajmp ret rl add code addr code addr a a data addr @r0 @r1 r0 r1 r2 r3 r4 r5 r6 r7 bit addr, code addr code addr code addr a a data addr @r0 @r1 r0 r1 r2 r3 r4 r5 r6 r7 bit addr, code addr code addr a a, #data
sda 525x semiconductor group 123 1998-04-08 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 add add add add add add add add add add add jnb acall reti rlc addc addc addc addc addc addc addc addc addc addc addc addc jc ajmp orl orl orl orl orl orl orl orl orl orl a, data addr a, @r0 a, @r1 a, r0 a, r1 a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 bit addr, code addr code addr a a, #data a, data addr a, @r0 a, @r1 a, r0 a, r1 a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 code addr code addr data addr., a data addr, #data a, #data a, data addr a, @r0 a, @r1 a, r0 a, r1 a, r2 a, r3 table 32 instruction opcodes in hexadecimal order (contd) hex code number of bytes mnemonic operands
sda 525x semiconductor group 124 1998-04-08 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 orl orl orl orl jnc acall anl anl anl anl anl anl anl anl anl anl anl anl anl anl jz ajmp xrl xrl xrl xrl xrl xrl xrl xrl xrl xrl xrl xrl xrl xrl jnz acall orl a, r4 a, r5 a, r6 a, r7 code addr code addr data addr, a data addr, #data a, #data a, data addr a, @r0 a, @r1 a, r0 a, r1 a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 code addr code addr. data addr, a data addr, #data a, #data a, data addr a, @r0 a, @r1 a, r0 a, r1 a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 code addr code addr c, bit addr table 32 instruction opcodes in hexadecimal order (contd) hex code number of bytes mnemonic operands
sda 525x semiconductor group 125 1998-04-08 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 1 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 3 2 2 2 2 2 2 2 2 2 2 3 2 2 1 2 2 1 1 1 1 jmp mov mov mov mov mov mov mov mov mov mov mov mov sjmp ajmp anl movc div mov mov mov mov mov mov mov mov mov mov mov mov acall mov movc subb subb subb subb subb subb @a + dptr a, #data data addr, #data @r0, #data @r1, #data r0, #data r1, #data r2, #data r3, #data r4, #data r5, #data r6, #data r7, #data code addr code addr c, bit addr a, @a + pc ab data addr, data addr data addr, @r0 data addr, @r1 data addr, r0 data addr, r1 data addr, r2 data addr, r3 data addr, r4 data addr, r5 data addr, r6 data addr, r7 dptr, #data 16 code addr bit addr, c a, @a + dptr a, #data a, data addr a, @r0 a, @r1 a, r0 a, r1 table 32 instruction opcodes in hexadecimal order (contd) hex code number of bytes mnemonic operands
sda 525x semiconductor group 126 1998-04-08 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf c0 1 1 1 1 1 1 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 3 3 3 3 3 3 3 3 3 3 3 2 subb subb subb subb subb subb orl ajmp mov inc mul reserved mov mov mov mov mov mov mov mov mov mov anl acall cpl cpl cjne cjne cjne cjne cjne cjne cjne cjne cjne cjne cjne cjne push a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 c, /bit addr code addr c, bit addr dptr ab @r0, data addr @r1, data addr r0, data addr r1, data addr r2, data addr r3, data addr r4, data addr r5, data addr r6, data addr r7, data addr c, /bit addr code addr bit addr c a, #data, code addr a, data addr, code addr @r0, #data, code addr @r1, #data, code addr r0, #data, code addr r1, #data, code addr r2, #data, code addr r3, #data, code addr r4, #data, code addr r5, #data, code addr r6, #data, code addr r7, #data, code addr data addr table 32 instruction opcodes in hexadecimal order (contd) hex code number of bytes mnemonic operands
sda 525x semiconductor group 127 1998-04-08 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5 e6 e7 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 3 2 2 2 2 2 2 2 2 1 2 1 2 1 1 ajmp clr clr swap xch xch xch xch xch xch xch xch xch xch xch pop acall setb setb da djnz not applicable not applicable djnz djnz djnz djnz djnz djnz djnz djnz movx ajmp not applicable not applicable clr mov mov mov code addr bit addr c a a, data addr a, @r0 a, @r1 a, r0 a, r1 a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 data addr code addr bit addr c a data addr, code addr r0, code addr r1, code addr r2, code addr r3, code addr r4, code addr r5, code addr r6, code addr r7, code addr a, @dptr code addr a a, data addr a, @r0 a, @r1 table 32 instruction opcodes in hexadecimal order (contd) hex code number of bytes mnemonic operands
sda 525x semiconductor group 128 1998-04-08 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 mov mov mov mov mov mov mov mov movx acall not applicable not applicable cpl mov mov mov mov mov mov mov mov mov mov mov a, r0 a, r1 a, r2 a, r3 a, r4 a, r5 a, r6 a, r7 @dptr, a code addr a data addr, a @r0, a @r1, a r0, a r1, a r2, a r3, a r4, a r5, a r6, a r7, a table 32 instruction opcodes in hexadecimal order (contd) hex code number of bytes mnemonic operands
sda 525x semiconductor group 129 1998-04-08 7 electrical characteristics 7.1 absolute maximum ratings 7.2 dc-characteristics table 33 parameter symbol limit values unit voltage on any pin with respect to ground ( v ss ) v s C 0.5 to 7 v power dissipation p tot 1w ambient temperature under bias t a 0 to 70 c storage temperature t stg C 65 to 125 c table 34 dc-characteristics t a = 0 to 70 c; v dd = 5 v 10 %, v ss = 0 v( c l = 80 pf) parameter symbol limit values units test condition min. max. l-input voltage (all except sc) v il C 0.5 0.8 v h-input voltage (all except xtal1, sc) v ih 2.0 v dd + 0.5 v h-input voltage (xtal1,lcin) v ih1 0.7 v dd v dd + 0.5 v l-output voltage v ol C 0.45 v i ol = 3.2 ma h-output voltage (ports 1 C 4 in port-mode) v oh 2.4 C v i oh = C 40 m a h-output voltage (all except ports in port-mode) v oh1 2.4 C v i oh = C1.6 ma logical 0 input current (ports 1 C 4, rst ,vs) i il1 C 50 m a v in = 0.45 v input leakage current (port 0, port 2, hs/sc) i li 1 m a 0.45 v v in v dd power supply current (sum of v dd - and v dda -pins) i dd 85 ma v dd = 5 v; f osc = 18 mhz idle current (sum of v dd - and v dda -pins) i idle 45 ma v dd = 5 v; f osc = 18 mhz
sda 525x semiconductor group 130 1998-04-08 1) adjustable, see chapter sandcastle decoder on page 33 and figure 41 . power down current (sum of v dd - and v dda -pins) i pd 1.5 ma v dd = 5 v pin capacitance c io 10 pf f c = 1 mhz h-sc voltage v sch 1) v dd + 0.5 v l-sc voltage 1 v scl1 C 0.5 1) v l-sc voltage 2 v scl2 1) 1) v analog input capacitance c i 45 pf adc-total unadjusted error tue t.b.d. lsb analog ground voltage v ssa v ss v ss v analog reference voltage v dda v dd v dd v analog input voltage v ai v ss C 0.2 v dd + 0.2 v video input signal level v cvbs 0.7 2.0 v synchron signal amplitude v sync 0.2 1.0 v data amplitude v dat 0.3 1.0 v table 34 dc-characteristics (contd) t a = 0 to 70 c; v dd = 5 v 10 %, v ss = 0 v( c l = 80 pf) parameter symbol limit values units test condition min. max.
sda 525x semiconductor group 131 1998-04-08 7.3 ac-characteristics external clock drive xtal1 / quartz clock drive xtal1 - xtal2 figure 39 external clock cycle table 35 t a = 0 to 70 c; v dd = 5 v 10 %, v ss = 0 v ( c l = 80 pf) parameter symbol limit values unit fixed internal clock 1/ t clcl = 18 mhz min. max. cycle time t cy 6 t clcl Cns address out to valid instr in t aviv C 2.3. x t clcl ns oscillator period t clcl 55.6 C ns external clock high time t chcx 13 C ns external clock low time t clcx 13 C ns external clock rise time t clch C13ns external clock fall time t chcl C13ns ued04735 chcx t 0.7 0.2 v dd dd v -0.1 -0.5 v dd t clcx clcl t t clch chcl t
sda 525x semiconductor group 132 1998-04-08 figure 40 program memory read cycle ued04734 ale inst in inst in inst in a0-16 a0-16 d a t cy alah t aviv t aliv t pxix t pxav t
sda 525x semiconductor group 133 1998-04-08 osd-input/output timing figure 41 osd-input/output timing table 36 parameter symbol limit values fixed dot clock f dot = 12 mhz unit min. max. l-sandcastle time t scl 15 m s h-sandcastle time t sch 3 m s horizontal offset t ho t sch m s pixel width t dot 83 ns sc uet05095 r, g, b, blan, cor vo t v sch v scl 2 scl 1 v t scl sch t t ho dot t line t
sda 525x semiconductor group 134 1998-04-08 display-generator-timing 1) default after reset is 2.8 m s; if bit 7 in sfr 0cd h is set, the second value is valid figure 42 horizontal sync-timing table 37 t a = 0 to 70 c; v dd = 5 v 10 %, v ss = 0 v parameter symbol limit values unit min. max. hsync width t hhhl 2.8 / 1.4 1) C m s end of visible screen area to hsync 1 t vlhh 0Cns start of visible screen area to hsync 0 t hlvh 0Cns delay between hsync and r/g/b/blan/cor-lines t hhcl 25 100 ns horizontal flyback visible area hs applied to sda525x t hhhl t vlhh t hlvh t hhcl r/g/b/blan/ cor
sda 525x semiconductor group 135 1998-04-08 ac-testing input, output, float waveforms ac testing inputs are driven at v dd C 0.5 v for a logic 1 and at 0.45 v for a logic 0. timing measurements are made at v ihmin for a logic 1 and at v ihmax for a logic 0. for timing purposes a port pin is no longer floating, when a 100 mv change from load voltage occurs. figure 43 i/o-waveform for ac-tests test points timing reference points ued04592 0.5 v dd v - v 0.45 - v oh v 0.1 0.9 dd v + 0.1 v load v + v load 0.2 0.2 - v dd 0.1 0.1 v ol v + - v load v 0.1
sda 525x semiconductor group 136 1998-04-08 8 applications figure 44 application circuit for 50 hz field frequency ued09863 33 pf 33 pf 10 f m sda 525x m 10 f 3 330 nf 18 mhz 82 k w +5 v r/g/b 470 k w w 6.8 k 33 nf sandcastle cvbs 150 pf 2.2 k w 8 4 8 8 i/o port 3 input port 2 (adc) i/o port 1 (pwm) i/o port 0 (open-drain) xtal1 xtal2 rst p0.0-7 p1.0-7 p2.0-3 p3.0-7 sc fil1 cvbs only romless ref i dd v ss v 33 nf fil2 w 8.2 k 220 nf fil3 39 pf 39 pf 6.8 lcin lcout max. tolerance of lc-circuit m h eprom a17, a18 d0...d7 a0...a16 d a (1 pp v ) 6.8 k w 2 blan/cor +5 v 8.2 k w
sda 525x semiconductor group 137 1998-04-08 9 package outlines 46.1 0.25 14.02 15.24 1.78 0.46 52 27 126 1.3 max 0.5 min 3.43 4.83 max -0.3 0.25 -0.4 0.05 0.1 0.25 max +1.7 index marking +0.7 15.24 m 0.25 52x p-sdip-52-1 plastic shrink dual in-line package gpd05262 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in m m smd = surface mounted device
sda 525x semiconductor group 138 1998-04-08 p-lcc-84-2 (plastic leaded chip carrier) gpl05620 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
sda 525x semiconductor group 139 1998-04-08 p-mqfp-64-1 (plastic metric quad flat package) gpm05250 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
sda 525x semiconductor group 140 1998-04-08 0.65 0.3 12.35 0.1 2 2.45 max 1 80 index marking 17.2 14 0.25 min +0.1 0.88 1) 0.6x45? 1) does not include plastic or metal protrusions of 0.25 max per side a-b 0.2 h d 4x a-b 0.2 d 80x a b d c 0.12 80x d a-b m c 1) 14 17.2 -0.05 h 7?max -0.02 +0.08 0.15 0.08 gpm05249 p-mqfp-80-1 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in m m smd = surface mounted device
semiconductor group 141 1998-04-08 sda 525x 10 index a acc, a 60 ac-characteristics 131 acqms_1 61 acqms_2 61 acqsir 19, 61 acquisition 5, 16 acquisition control registers 18 acquisition hardware 16 acquistion mode and status register 18 adc-control register 114 adc-data register 115 adcon 61, 114 adc-start register 113 addat 61, 115 addressing modes 47 advanced function register 89, 115 afr 89, 115 analog digital converter 61 applications 136 architecture 42 arithmetic operations 117 arithmetic registers 60 b b 60 banking 50 base-register plus index register-indirect addressing 48 baud rates 94 block diagram 7 boolean variable manipulation 120 c caph 60 capl 60 capture compare timer 46, 90 capture compare timer registers 60 character generator 22 clear page logic 20 cpu-hardware 43 cpu-timing 46 d dapr 61, 113 data pointer 45 data transfer operations 119 dc-characteristics 129 dccp 62 dcrp 62 dhd 62 direct addressing 48 display 5 display control registers 62 display cursor 20 display format and timing 20 display generator 20 display page addressing 21 display special function registers 24 display-generator-timing 133 dmod 62 dmode1 62 dmode2 62 double size 26 double width 26 dph 60 dpl 60 dpsel 60 dptr 45 dtcr 62 dtim 62 dvd 62 e external interrupts 72 f features 5 flash 20 full screen background colour 20 functional description 16 g general purpose timers/counters 80 h horizontal sync-timing 134
semiconductor group 142 1998-04-08 sda 525x i i/o-port registers 60 ie 60 immediate addressing 48 infrared timer control register 90 instruction opcodes in hexadecimal order 122 instruction set 116 instruction set description 117 internal data memory address space 57 internal data ram 43, 55 interrupt control 63 interrupt control registers 60 interrupt logic 45 interrupt nesting 71 interrupt sources 62 interrupt system 62, 66 ip0 60 ip1 60 ircon 60 irtcon 60 l langc 29, 62 language control register 29 logical operations 118 m memory extension 50 memory interface 17 memory organization 49 microcontroller 6, 42 multiprocessor communication 93 o on screen display 22 osd 22 osd-input/output timing 133 p p0 60 p1 60 p2 60 p3 60 p4 60 package outlines 137 pcon 60, 77 pin configuration 8 pin functions 12 plastic package 137 p-lcc-84-2 138 p-lcc-84-2 package 6 p-mqfp-64-1 6, 139 p-mqfp-80-1 140 p-mqfp-80-1 package 6 port 0 45 port 1 45 port 2 45 port 3 45 port 4 45 ports and i/o-pins 78 power control register 77 power-down operations 76 priority within level 71 processor reset 75 program and machine control operations 121 program memory 49 program status word 44 p-sdip-52-1 137 p-sdip-52-1 package 6 psw 44, 60 pulse width modulation unit 46, 106 pulse width modulator registers 61 pwch 61, 111 pwcl 61 pwcomp 0-5 108 pwcomp0 61 pwcomp1 61 pwcomp2 61 pwcomp3 61 pwcomp4 61 pwcomp5 61 pwcomp6 61 pwcomp7 61 pwext6 61 pwext7 61 pwm 106
semiconductor group 143 1998-04-08 sda 525x pwm compare registers 108 pwm high counter registers 111 pwme 61, 108 pwm-enable register 108 r read-modify-write 80 register addressing 48 register-indirect addressing 48 relh 60 rell 60 response time 74 s sandcastle control register 33 sandcastle decoder 33 sbuf 61 sccon 33, 62 scon 61, 92 serial interface 45, 91 serial interface registers 61 serial port control register 92 serial port mode 0 98 serial port mode 1 100 serial port mode 2 102 serial port mode 3 104 serial port mode selection 93 slicer control registers 61 sp 45, 60 special function register bit address space 59 special function register overview 60 stack pointer 45 synchronisation 6 system control registers 60 t tcon 60 teletext sync interrupt request register 67 teletext sync signal interrupt system 65 teletext-sync-interrupt-register 32 th0 60 th1 60 timer 0/1 registers 60 timer/counter 0 81 timer/counter 0/1 45 timer/counter 1 82 tl0 60 tl1 60 tmod 60, 83, 84 ttxsir 62, 67 v vtx/vps slicer 16 w watchdog timer 46, 87 watchdog timer control register 88 watchdog timer registers 60 watchdog timer reload register 88 waveforms 135 wdcon 60 wdth 60 wdtl 60 wdtrel 60, 88

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